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<section id="mpic-interrupt-controller">
<h1>MPIC interrupt controller<a class="headerlink" href="#mpic-interrupt-controller" title="Link to this heading">¶</a></h1>
<p>Device types supported:</p>
<blockquote>
<div><ul class="simple">
<li><p>KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0</p></li>
<li><p>KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2</p></li>
</ul>
</div></blockquote>
<p>Only one MPIC instance, of any type, may be instantiated. The created
MPIC will act as the system interrupt controller, connecting to each
vcpu’s interrupt inputs.</p>
<dl>
<dt>Groups:</dt><dd><dl>
<dt>KVM_DEV_MPIC_GRP_MISC</dt><dd><p>Attributes:</p>
<blockquote>
<div><dl class="simple">
<dt>KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)</dt><dd><p>Base address of the 256 KiB MPIC register space. Must be
naturally aligned. A value of zero disables the mapping.
Reset value is zero.</p>
</dd>
</dl>
</div></blockquote>
</dd>
<dt>KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)</dt><dd><p>Access an MPIC register, as if the access were made from the guest.
“attr” is the byte offset into the MPIC register space. Accesses
must be 4-byte aligned.</p>
<p>MSIs may be signaled by using this attribute group to write
to the relevant MSIIR.</p>
</dd>
<dt>KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)</dt><dd><p>IRQ input line for each standard openpic source. 0 is inactive and 1
is active, regardless of interrupt sense.</p>
<p>For edge-triggered interrupts: Writing 1 is considered an activating
edge, and writing 0 is ignored. Reading returns 1 if a previously
signaled edge has not been acknowledged, and 0 otherwise.</p>
<p>“attr” is the IRQ number. IRQ numbers for standard sources are the
byte offset of the relevant IVPR from EIVPR0, divided by 32.</p>
</dd>
</dl>
</dd>
</dl>
<p>IRQ Routing:</p>
<blockquote>
<div><p>The MPIC emulation supports IRQ routing. Only a single MPIC device can
be instantiated. Once that device has been created, it’s available as
irqchip id 0.</p>
<p>This irqchip 0 has 256 interrupt pins, which expose the interrupts in
the main array of interrupt sources (a.k.a. “SRC” interrupts).</p>
<p>The numbering is the same as the MPIC device tree binding -- based on
the register offset from the beginning of the sources array, without
regard to any subdivisions in chip documentation such as “internal”
or “external” interrupts.</p>
<p>Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.</p>
</div></blockquote>
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