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<section id="highpoint-rocketraid-3xxx-4xxx-adapter-driver-hptiop">
<h1>Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)<a class="headerlink" href="#highpoint-rocketraid-3xxx-4xxx-adapter-driver-hptiop" title="Link to this heading">¶</a></h1>
<section id="controller-register-map">
<h2>Controller Register Map<a class="headerlink" href="#controller-register-map" title="Link to this heading">¶</a></h2>
<p>For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2</p>
<blockquote>
<div><table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR0 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x11C5C</p></td>
<td><p>Link Interface IRQ Set</p></td>
</tr>
<tr class="row-odd"><td><p>0x11C60</p></td>
<td><p>Link Interface IRQ Clear</p></td>
</tr>
</tbody>
</table>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR2 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x10</p></td>
<td><p>Inbound Message Register 0</p></td>
</tr>
<tr class="row-odd"><td><p>0x14</p></td>
<td><p>Inbound Message Register 1</p></td>
</tr>
<tr class="row-even"><td><p>0x18</p></td>
<td><p>Outbound Message Register 0</p></td>
</tr>
<tr class="row-odd"><td><p>0x1C</p></td>
<td><p>Outbound Message Register 1</p></td>
</tr>
<tr class="row-even"><td><p>0x20</p></td>
<td><p>Inbound Doorbell Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x24</p></td>
<td><p>Inbound Interrupt Status Register</p></td>
</tr>
<tr class="row-even"><td><p>0x28</p></td>
<td><p>Inbound Interrupt Mask Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x30</p></td>
<td><p>Outbound Interrupt Status Register</p></td>
</tr>
<tr class="row-even"><td><p>0x34</p></td>
<td><p>Outbound Interrupt Mask Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x40</p></td>
<td><p>Inbound Queue Port</p></td>
</tr>
<tr class="row-even"><td><p>0x44</p></td>
<td><p>Outbound Queue Port</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:</p>
<blockquote>
<div><table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR0 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x10</p></td>
<td><p>Inbound Message Register 0</p></td>
</tr>
<tr class="row-odd"><td><p>0x14</p></td>
<td><p>Inbound Message Register 1</p></td>
</tr>
<tr class="row-even"><td><p>0x18</p></td>
<td><p>Outbound Message Register 0</p></td>
</tr>
<tr class="row-odd"><td><p>0x1C</p></td>
<td><p>Outbound Message Register 1</p></td>
</tr>
<tr class="row-even"><td><p>0x20</p></td>
<td><p>Inbound Doorbell Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x24</p></td>
<td><p>Inbound Interrupt Status Register</p></td>
</tr>
<tr class="row-even"><td><p>0x28</p></td>
<td><p>Inbound Interrupt Mask Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x30</p></td>
<td><p>Outbound Interrupt Status Register</p></td>
</tr>
<tr class="row-even"><td><p>0x34</p></td>
<td><p>Outbound Interrupt Mask Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x40</p></td>
<td><p>Inbound Queue Port</p></td>
</tr>
<tr class="row-even"><td><p>0x44</p></td>
<td><p>Outbound Queue Port</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:</p>
<blockquote>
<div><table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR0 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x20400</p></td>
<td><p>Inbound Doorbell Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x20404</p></td>
<td><p>Inbound Interrupt Mask Register</p></td>
</tr>
<tr class="row-even"><td><p>0x20408</p></td>
<td><p>Outbound Doorbell Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x2040C</p></td>
<td><p>Outbound Interrupt Mask Register</p></td>
</tr>
</tbody>
</table>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR1 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x0</p></td>
<td><p>Inbound Queue Head Pointer</p></td>
</tr>
<tr class="row-odd"><td><p>0x4</p></td>
<td><p>Inbound Queue Tail Pointer</p></td>
</tr>
<tr class="row-even"><td><p>0x8</p></td>
<td><p>Outbound Queue Head Pointer</p></td>
</tr>
<tr class="row-odd"><td><p>0xC</p></td>
<td><p>Outbound Queue Tail Pointer</p></td>
</tr>
<tr class="row-even"><td><p>0x10</p></td>
<td><p>Inbound Message Register</p></td>
</tr>
<tr class="row-odd"><td><p>0x14</p></td>
<td><p>Outbound Message Register</p></td>
</tr>
<tr class="row-even"><td><p>0x40-0x1040</p></td>
<td><p>Inbound Queue</p></td>
</tr>
<tr class="row-odd"><td><p>0x1040-0x2040</p></td>
<td><p>Outbound Queue</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:</p>
<blockquote>
<div><table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR0 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x0</p></td>
<td><p>IOP configuration information.</p></td>
</tr>
</tbody>
</table>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>BAR1 offset</p></th>
<th class="head"><p>Register</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x4000</p></td>
<td><p>Inbound List Base Address Low</p></td>
</tr>
<tr class="row-odd"><td><p>0x4004</p></td>
<td><p>Inbound List Base Address High</p></td>
</tr>
<tr class="row-even"><td><p>0x4018</p></td>
<td><p>Inbound List Write Pointer</p></td>
</tr>
<tr class="row-odd"><td><p>0x402C</p></td>
<td><p>Inbound List Configuration and Control</p></td>
</tr>
<tr class="row-even"><td><p>0x4050</p></td>
<td><p>Outbound List Base Address Low</p></td>
</tr>
<tr class="row-odd"><td><p>0x4054</p></td>
<td><p>Outbound List Base Address High</p></td>
</tr>
<tr class="row-even"><td><p>0x4058</p></td>
<td><p>Outbound List Copy Pointer Shadow Base Address Low</p></td>
</tr>
<tr class="row-odd"><td><p>0x405C</p></td>
<td><p>Outbound List Copy Pointer Shadow Base Address High</p></td>
</tr>
<tr class="row-even"><td><p>0x4088</p></td>
<td><p>Outbound List Interrupt Cause</p></td>
</tr>
<tr class="row-odd"><td><p>0x408C</p></td>
<td><p>Outbound List Interrupt Enable</p></td>
</tr>
<tr class="row-even"><td><p>0x1020C</p></td>
<td><p>PCIe Function 0 Interrupt Enable</p></td>
</tr>
<tr class="row-odd"><td><p>0x10400</p></td>
<td><p>PCIe Function 0 to CPU Message A</p></td>
</tr>
<tr class="row-even"><td><p>0x10420</p></td>
<td><p>CPU to PCIe Function 0 Message A</p></td>
</tr>
<tr class="row-odd"><td><p>0x10480</p></td>
<td><p>CPU to PCIe Function 0 Doorbell</p></td>
</tr>
<tr class="row-even"><td><p>0x10484</p></td>
<td><p>CPU to PCIe Function 0 Doorbell Enable</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
</section>
<section id="i-o-request-workflow-of-not-marvell-frey">
<h2>I/O Request Workflow of Not Marvell Frey<a class="headerlink" href="#i-o-request-workflow-of-not-marvell-frey" title="Link to this heading">¶</a></h2>
<p>All queued requests are handled via inbound/outbound queue port.
A request packet can be allocated in either IOP or host memory.</p>
<p>To send a request to the controller:</p>
<blockquote>
<div><ul>
<li><p>Get a free request packet by reading the inbound queue port or
allocate a free request in host DMA coherent memory.</p>
<p>The value returned from the inbound queue port is an offset
relative to the IOP BAR0.</p>
<p>Requests allocated in host memory must be aligned on 32-bytes boundary.</p>
</li>
<li><p>Fill the packet.</p></li>
<li><p>Post the packet to IOP by writing it to inbound queue. For requests
allocated in IOP memory, write the offset to inbound queue port. For
requests allocated in host memory, write (0x80000000|(bus_addr&gt;&gt;5))
to the inbound queue port.</p></li>
<li><p>The IOP process the request. When the request is completed, it
will be put into outbound queue. An outbound interrupt will be
generated.</p>
<p>For requests allocated in IOP memory, the request offset is posted to
outbound queue.</p>
<p>For requests allocated in host memory, (0x80000000|(bus_addr&gt;&gt;5))
is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT
flag is set in the request, the low 32-bit context value will be
posted instead.</p>
</li>
<li><p>The host read the outbound queue and complete the request.</p>
<p>For requests allocated in IOP memory, the host driver free the request
by writing it to the outbound queue.</p>
</li>
</ul>
</div></blockquote>
<p>Non-queued requests (reset/flush etc) can be sent via inbound message
register 0. An outbound message with the same value indicates the completion
of an inbound message.</p>
</section>
<section id="i-o-request-workflow-of-marvell-frey">
<h2>I/O Request Workflow of Marvell Frey<a class="headerlink" href="#i-o-request-workflow-of-marvell-frey" title="Link to this heading">¶</a></h2>
<p>All queued requests are handled via inbound/outbound list.</p>
<p>To send a request to the controller:</p>
<blockquote>
<div><ul>
<li><p>Allocate a free request in host DMA coherent memory.</p>
<p>Requests allocated in host memory must be aligned on 32-bytes boundary.</p>
</li>
<li><p>Fill the request with index of the request in the flag.</p>
<p>Fill a free inbound list unit with the physical address and the size of
the request.</p>
<p>Set up the inbound list write pointer with the index of previous unit,
round to 0 if the index reaches the supported count of requests.</p>
</li>
<li><p>Post the inbound list writer pointer to IOP.</p></li>
<li><p>The IOP process the request. When the request is completed, the flag of
the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
free outbound list unit and the index of the outbound list unit will be
put into the copy pointer shadow register. An outbound interrupt will be
generated.</p></li>
<li><p>The host read the outbound list copy pointer shadow register and compare
with previous saved read pointer N. If they are different, the host will
read the (N+1)th outbound list unit.</p>
<p>The host get the index of the request from the (N+1)th outbound list
unit and complete the request.</p>
</li>
</ul>
</div></blockquote>
<p>Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
with the same value indicates the completion of message.</p>
</section>
<section id="user-level-interface">
<h2>User-level Interface<a class="headerlink" href="#user-level-interface" title="Link to this heading">¶</a></h2>
<p>The driver exposes following sysfs attributes:</p>
<blockquote>
<div><table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>NAME</p></th>
<th class="head"><p>R/W</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>driver-version</p></td>
<td><p>R</p></td>
<td><p>driver version string</p></td>
</tr>
<tr class="row-odd"><td><p>firmware-version</p></td>
<td><p>R</p></td>
<td><p>firmware version string</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<hr class="docutils" />
<p>Copyright © 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.</p>
<blockquote>
<div><p>This file is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.</p>
<p><a class="reference external" href="mailto:linux&#37;&#52;&#48;highpoint-tech&#46;com">linux<span>&#64;</span>highpoint-tech<span>&#46;</span>com</a></p>
<p><a class="reference external" href="http://www.highpoint-tech.com">http://www.highpoint-tech.com</a></p>
</div></blockquote>
</section>
</section>


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