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<section id="drm-meson-amlogic-meson-video-processing-unit">
<h1>drm/meson AmLogic Meson Video Processing Unit<a class="headerlink" href="#drm-meson-amlogic-meson-video-processing-unit" title="Link to this heading">¶</a></h1>
<p>VPU Handles the Global Video Processing, it includes management of the
clocks gates, blocks reset lines and power domains.</p>
<p>What is missing :</p>
<ul class="simple">
<li><p>Full reset of entire video processing HW blocks</p></li>
<li><p>Scaling and setup of the VPU clock</p></li>
<li><p>Bus clock gates</p></li>
<li><p>Powering up video processing HW blocks</p></li>
<li><p>Powering Up HDMI controller and PHY</p></li>
</ul>
<section id="video-processing-unit">
<h2>Video Processing Unit<a class="headerlink" href="#video-processing-unit" title="Link to this heading">¶</a></h2>
<p>The Amlogic Meson Display controller is composed of several components
that are going to be documented below:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
| vd1 _______ _____________ _________________ | |
D |-------| |----| | | | | HDMI PLL |
D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
R |-------| |----| Processing | | | | |
| osd2 | | | |---| Enci ----------|----|-----VDAC------|
R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
A | osd1 | | | Blenders | | Encl ----------|----|---------------|
M |-------|______|----|____________| |________________| | |
___|__________________________________________________________|_______________|
</pre></div>
</div>
</section>
<section id="video-input-unit">
<h2>Video Input Unit<a class="headerlink" href="#video-input-unit" title="Link to this heading">¶</a></h2>
<p>VIU Handles the Pixel scanout and the basic Colorspace conversions
We handle the following features :</p>
<ul class="simple">
<li><p>OSD1 RGB565/RGB888/xRGB8888 scanout</p></li>
<li><p>RGB conversion to x/cb/cr</p></li>
<li><p>Progressive or Interlace buffer scanout</p></li>
<li><p>OSD1 Commit on Vsync</p></li>
<li><p>HDR OSD matrix for GXL/GXM</p></li>
</ul>
<p>What is missing :</p>
<ul class="simple">
<li><p>BGR888/xBGR8888/BGRx8888/BGRx8888 modes</p></li>
<li><p>YUV4:2:2 Y0CbY1Cr scanout</p></li>
<li><p>Conversion to YUV 4:4:4 from 4:2:2 input</p></li>
<li><p>Colorkey Alpha matching</p></li>
<li><p>Big endian scanout</p></li>
<li><p>X/Y reverse scanout</p></li>
<li><p>Global alpha setup</p></li>
<li><p>OSD2 support, would need interlace switching on vsync</p></li>
<li><p>OSD1 full scaling to support TV overscan</p></li>
</ul>
</section>
<section id="video-post-processing">
<h2>Video Post Processing<a class="headerlink" href="#video-post-processing" title="Link to this heading">¶</a></h2>
<p>VPP Handles all the Post Processing after the Scanout from the VIU
We handle the following post processings :</p>
<ul class="simple">
<li><dl class="simple">
<dt>Postblend, Blends the OSD1 only</dt><dd><p>We exclude OSD2, VS1, VS1 and Preblend output</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt>Vertical OSD Scaler for OSD1 only, we disable vertical scaler and</dt><dd><p>use it only for interlace scanout</p>
</dd>
</dl>
</li>
<li><p>Intermediate FIFO with default Amlogic values</p></li>
</ul>
<p>What is missing :</p>
<ul class="simple">
<li><p>Preblend for video overlay pre-scaling</p></li>
<li><p>OSD2 support for cursor framebuffer</p></li>
<li><p>Video pre-scaling before postblend</p></li>
<li><p>Full Vertical/Horizontal OSD scaling to support TV overscan</p></li>
<li><p>HDR conversion</p></li>
</ul>
</section>
<section id="video-encoder">
<h2>Video Encoder<a class="headerlink" href="#video-encoder" title="Link to this heading">¶</a></h2>
<p>VENC Handle the pixels encoding to the output formats.
We handle the following encodings :</p>
<ul class="simple">
<li><p>CVBS Encoding via the ENCI encoder and VDAC digital to analog converter</p></li>
<li><p>TMDS/HDMI Encoding via ENCI_DIV and ENCP</p></li>
<li><p>Setup of more clock rates for HDMI modes</p></li>
</ul>
<p>What is missing :</p>
<ul class="simple">
<li><p>LCD Panel encoding via ENCL</p></li>
<li><p>TV Panel encoding via ENCT</p></li>
</ul>
<p>VENC paths :</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span> _____ _____ ____________________
vd1---| |-| | | VENC /---------|----VDAC
vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
osd1--| |-| | | \ | X--HDMI-TX
osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
| | |
| \--ENCL-----------|----LVDS
|____________________|
</pre></div>
</div>
<p>The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
The ENCP is designed for Progressive encoding but can also generate
1080i interlaced pixels, and was initially designed to encode pixels for
VDAC to output RGB ou YUV analog outputs.
It’s output is only used through the ENCP_DVI encoder for HDMI.
The ENCL LVDS encoder is not implemented.</p>
<p>The ENCI and ENCP encoders needs specially defined parameters for each
supported mode and thus cannot be determined from standard video timings.</p>
<p>The ENCI end ENCP DVI encoders are more generic and can generate any timings
from the pixel data generated by ENCI or ENCP, so can use the standard video
timings are source for HW parameters.</p>
</section>
<section id="video-clocks">
<h2>Video Clocks<a class="headerlink" href="#video-clocks" title="Link to this heading">¶</a></h2>
<p>VCLK is the “Pixel Clock” frequency generator from a dedicated PLL.
We handle the following encodings :</p>
<ul class="simple">
<li><p>CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks</p></li>
<li><p>HDMI Pixel Clocks generation</p></li>
</ul>
<p>What is missing :</p>
<ul class="simple">
<li><p>Genenate Pixel clocks for 2K/4K 10bit formats</p></li>
</ul>
<p>Clock generator scheme :</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span> __________ _________ _____
| | | | | |--ENCI
| HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
|__________| |_________| \ | MUX |--ENCP
--VCLK2-| |--VDAC
|_____|--HDMI-TX
</pre></div>
</div>
<p>Final clocks can take input for either VCLK or VCLK2, but
VCLK is the preferred path for HDMI clocking and VCLK2 is the
preferred path for CVBS VDAC clocking.</p>
<p>VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.</p>
<p>The PLL_DIV can achieve an additional fractional dividing like
1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.</p>
</section>
<section id="hdmi-video-output">
<h2>HDMI Video Output<a class="headerlink" href="#hdmi-video-output" title="Link to this heading">¶</a></h2>
<p>HDMI Output is composed of :</p>
<ul class="simple">
<li><p>A Synopsys DesignWare HDMI Controller IP</p></li>
<li><p>A TOP control block controlling the Clocks and PHY</p></li>
<li><p>A custom HDMI PHY in order convert video to TMDS signal</p></li>
</ul>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span> ___________________________________
| HDMI TOP |<= HPD
|___________________________________|
| | |
| Synopsys HDMI | HDMI PHY |=> TMDS
| Controller |________________|
|___________________________________|<=> DDC
</pre></div>
</div>
<p>The HDMI TOP block only supports HPD sensing.
The Synopsys HDMI Controller interrupt is routed
through the TOP Block interrupt.
Communication to the TOP Block and the Synopsys
HDMI Controller is done a pair of addr+read/write
registers.
The HDMI PHY is configured by registers in the
HHI register block.</p>
<p>Pixel data arrives in 4:4:4 format from the VENC
block and the VPU HDMI mux selects either the ENCI
encoder for the 576i or 480i formats or the ENCP
encoder for all the other formats including
interlaced HD formats.
The VENC uses a DVI encoder on top of the ENCI
or ENCP encoders to generate DVI timings for the
HDMI controller.</p>
<p>GXBB, GXL and GXM embeds the Synopsys DesignWare
HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
audio source interfaces.</p>
<p>We handle the following features :</p>
<ul class="simple">
<li><p>HPD Rise & Fall interrupt</p></li>
<li><p>HDMI Controller Interrupt</p></li>
<li><p>HDMI PHY Init for 480i to 1080p60</p></li>
<li><p>VENC & HDMI Clock setup for 480i to 1080p60</p></li>
<li><p>VENC Mode setup for 480i to 1080p60</p></li>
</ul>
<p>What is missing :</p>
<ul class="simple">
<li><p>PHY, Clock and Mode setup for 2k && 4k modes</p></li>
<li><p>SDDC Scrambling mode for HDMI 2.0a</p></li>
<li><p>HDCP Setup</p></li>
<li><p>CEC Management</p></li>
</ul>
</section>
</section>
</div>
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