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<section id="microarchitectural-data-sampling-mds-mitigation">
<h1><span class="section-number">24. </span>Microarchitectural Data Sampling (MDS) mitigation<a class="headerlink" href="#microarchitectural-data-sampling-mds-mitigation" title="Link to this heading">¶</a></h1>
<section id="overview">
<span id="mds"></span><h2><span class="section-number">24.1. </span>Overview<a class="headerlink" href="#overview" title="Link to this heading">¶</a></h2>
<p>Microarchitectural Data Sampling (MDS) is a family of side channel attacks
on internal buffers in Intel CPUs. The variants are:</p>
<blockquote>
<div><ul class="simple">
<li><p>Microarchitectural Store Buffer Data Sampling (MSBDS) (CVE-2018-12126)</p></li>
<li><p>Microarchitectural Fill Buffer Data Sampling (MFBDS) (CVE-2018-12130)</p></li>
<li><p>Microarchitectural Load Port Data Sampling (MLPDS) (CVE-2018-12127)</p></li>
<li><p>Microarchitectural Data Sampling Uncacheable Memory (MDSUM) (CVE-2019-11091)</p></li>
</ul>
</div></blockquote>
<p>MSBDS leaks Store Buffer Entries which can be speculatively forwarded to a
dependent load (store-to-load forwarding) as an optimization. The forward
can also happen to a faulting or assisting load operation for a different
memory address, which can be exploited under certain conditions. Store
buffers are partitioned between Hyper-Threads so cross thread forwarding is
not possible. But if a thread enters or exits a sleep state the store
buffer is repartitioned which can expose data from one thread to the other.</p>
<p>MFBDS leaks Fill Buffer Entries. Fill buffers are used internally to manage
L1 miss situations and to hold data which is returned or sent in response
to a memory or I/O operation. Fill buffers can forward data to a load
operation and also write data to the cache. When the fill buffer is
deallocated it can retain the stale data of the preceding operations which
can then be forwarded to a faulting or assisting load operation, which can
be exploited under certain conditions. Fill buffers are shared between
Hyper-Threads so cross thread leakage is possible.</p>
<p>MLPDS leaks Load Port Data. Load ports are used to perform load operations
from memory or I/O. The received data is then forwarded to the register
file or a subsequent operation. In some implementations the Load Port can
contain stale data from a previous operation which can be forwarded to
faulting or assisting loads under certain conditions, which again can be
exploited eventually. Load ports are shared between Hyper-Threads so cross
thread leakage is possible.</p>
<p>MDSUM is a special case of MSBDS, MFBDS and MLPDS. An uncacheable load from
memory that takes a fault or assist can leave data in a microarchitectural
structure that may later be observed using one of the same methods used by
MSBDS, MFBDS or MLPDS.</p>
</section>
<section id="exposure-assumptions">
<h2><span class="section-number">24.2. </span>Exposure assumptions<a class="headerlink" href="#exposure-assumptions" title="Link to this heading">¶</a></h2>
<p>It is assumed that attack code resides in user space or in a guest with one
exception. The rationale behind this assumption is that the code construct
needed for exploiting MDS requires:</p>
<blockquote>
<div><ul class="simple">
<li><p>to control the load to trigger a fault or assist</p></li>
<li><p>to have a disclosure gadget which exposes the speculatively accessed
data for consumption through a side channel.</p></li>
<li><p>to control the pointer through which the disclosure gadget exposes the
data</p></li>
</ul>
</div></blockquote>
<p>The existence of such a construct in the kernel cannot be excluded with
100% certainty, but the complexity involved makes it extremely unlikely.</p>
<p>There is one exception, which is untrusted BPF. The functionality of
untrusted BPF is limited, but it needs to be thoroughly investigated
whether it can be used to create such a construct.</p>
</section>
<section id="mitigation-strategy">
<h2><span class="section-number">24.3. </span>Mitigation strategy<a class="headerlink" href="#mitigation-strategy" title="Link to this heading">¶</a></h2>
<p>All variants have the same mitigation strategy at least for the single CPU
thread case (SMT off): Force the CPU to clear the affected buffers.</p>
<p>This is achieved by using the otherwise unused and obsolete VERW
instruction in combination with a microcode update. The microcode clears
the affected CPU buffers when the VERW instruction is executed.</p>
<p>For virtualization there are two ways to achieve CPU buffer
clearing. Either the modified VERW instruction or via the L1D Flush
command. The latter is issued when L1TF mitigation is enabled so the extra
VERW can be avoided. If the CPU is not affected by L1TF then VERW needs to
be issued.</p>
<p>If the VERW instruction with the supplied segment selector argument is
executed on a CPU without the microcode update there is no side effect
other than a small number of pointlessly wasted CPU cycles.</p>
<p>This does not protect against cross Hyper-Thread attacks except for MSBDS
which is only exploitable cross Hyper-thread when one of the Hyper-Threads
enters a C-state.</p>
<p>The kernel provides a function to invoke the buffer clearing:</p>
<blockquote>
<div><p><code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">x86_clear_cpu_buffers()</span></code></p>
</div></blockquote>
<p>Also macro CLEAR_CPU_BUFFERS can be used in ASM late in exit-to-user path.
Other than CFLAGS.ZF, this macro doesn’t clobber any registers.</p>
<p>The mitigation is invoked on kernel/userspace, hypervisor/guest and C-state
(idle) transitions.</p>
<p>As a special quirk to address virtualization scenarios where the host has
the microcode updated, but the hypervisor does not (yet) expose the
MD_CLEAR CPUID bit to guests, the kernel issues the VERW instruction in the
hope that it might actually clear the buffers. The state is reflected
accordingly.</p>
<p>According to current knowledge additional mitigations inside the kernel
itself are not required because the necessary gadgets to expose the leaked
data cannot be controlled in a way which allows exploitation from malicious
user space or VM guests.</p>
</section>
<section id="kernel-internal-mitigation-modes">
<h2><span class="section-number">24.4. </span>Kernel internal mitigation modes<a class="headerlink" href="#kernel-internal-mitigation-modes" title="Link to this heading">¶</a></h2>
<blockquote>
<div><table class="docutils align-default">
<tbody>
<tr class="row-odd"><td><p>off</p></td>
<td><p>Mitigation is disabled. Either the CPU is not affected or
mds=off is supplied on the kernel command line</p></td>
</tr>
<tr class="row-even"><td><p>full</p></td>
<td><p>Mitigation is enabled. CPU is affected and MD_CLEAR is
advertised in CPUID.</p></td>
</tr>
<tr class="row-odd"><td><p>vmwerv</p></td>
<td><p>Mitigation is enabled. CPU is affected and MD_CLEAR is not
advertised in CPUID. That is mainly for virtualization
scenarios where the host has the updated microcode but the
hypervisor does not expose MD_CLEAR in CPUID. It’s a best
effort approach without guarantee.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>If the CPU is affected and mds=off is not supplied on the kernel command
line then the kernel selects the appropriate mitigation mode depending on
the availability of the MD_CLEAR CPUID bit.</p>
</section>
<section id="mitigation-points">
<h2><span class="section-number">24.5. </span>Mitigation points<a class="headerlink" href="#mitigation-points" title="Link to this heading">¶</a></h2>
<section id="return-to-user-space">
<h3><span class="section-number">24.5.1. </span>1. Return to user space<a class="headerlink" href="#return-to-user-space" title="Link to this heading">¶</a></h3>
<blockquote>
<div><p>When transitioning from kernel to user space the CPU buffers are flushed
on affected CPUs when the mitigation is not disabled on the kernel
command line. The mitigation is enabled through the feature flag
X86_FEATURE_CLEAR_CPU_BUF.</p>
<p>The mitigation is invoked just before transitioning to userspace after
user registers are restored. This is done to minimize the window in
which kernel data could be accessed after VERW e.g. via an NMI after
VERW.</p>
<p><strong>Corner case not handled</strong>
Interrupts returning to kernel don’t clear CPUs buffers since the
exit-to-user path is expected to do that anyways. But, there could be
a case when an NMI is generated in kernel after the exit-to-user path
has cleared the buffers. This case is not handled and NMI returning to
kernel don’t clear CPU buffers because:</p>
<ol class="arabic simple">
<li><p>It is rare to get an NMI after VERW, but before returning to userspace.</p></li>
<li><p>For an unprivileged user, there is no known way to make that NMI
less rare or target it.</p></li>
<li><p>It would take a large number of these precisely-timed NMIs to mount
an actual attack.  There’s presumably not enough bandwidth.</p></li>
<li><p>The NMI in question occurs after a VERW, i.e. when user state is
restored and most interesting data is already scrubbed. What’s left
is only the data that NMI touches, and that may or may not be of
any interest.</p></li>
</ol>
</div></blockquote>
</section>
<section id="c-state-transition">
<h3><span class="section-number">24.5.2. </span>2. C-State transition<a class="headerlink" href="#c-state-transition" title="Link to this heading">¶</a></h3>
<blockquote>
<div><p>When a CPU goes idle and enters a C-State the CPU buffers need to be
cleared on affected CPUs when SMT is active. This addresses the
repartitioning of the store buffer when one of the Hyper-Threads enters
a C-State.</p>
<p>When SMT is inactive, i.e. either the CPU does not support it or all
sibling threads are offline CPU buffer clearing is not required.</p>
<p>The idle clearing is enabled on CPUs which are only affected by MSBDS
and not by any other MDS variant. The other MDS variants cannot be
protected against cross Hyper-Thread attacks because the Fill Buffer and
the Load Ports are shared. So on CPUs affected by other variants, the
idle clearing would be a window dressing exercise and is therefore not
activated.</p>
<p>The invocation is controlled by the static key cpu_buf_idle_clear which is
switched depending on the chosen mitigation mode and the SMT state of the
system.</p>
<p>The buffer clear is only invoked before entering the C-State to prevent
that stale data from the idling CPU from spilling to the Hyper-Thread
sibling after the store buffer got repartitioned and all entries are
available to the non idle sibling.</p>
<p>When coming out of idle the store buffer is partitioned again so each
sibling has half of it available. The back from idle CPU could be then
speculatively exposed to contents of the sibling. The buffers are
flushed either on exit to user space or on VMENTER so malicious code
in user space or the guest cannot speculatively access them.</p>
<p>The mitigation is hooked into all variants of <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">halt()</span></code>/<code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">mwait()</span></code>, but does
not cover the legacy ACPI IO-Port mechanism because the ACPI idle driver
has been superseded by the intel_idle driver around 2010 and is
preferred on all affected CPUs which are expected to gain the MD_CLEAR
functionality in microcode. Aside of that the IO-Port mechanism is a
legacy interface which is only used on older systems which are either
not affected or do not receive microcode updates anymore.</p>
</div></blockquote>
</section>
</section>
</section>


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DIR : / usr/ share/ doc/ linux-doc-6.18/ html/ arch/ x86/
Name Type Size Permission Actions
i386 Folder 0755
x86_64 Folder 0755
amd-debugging.html File 37.71 KB 0644
amd-hfi.html File 23.59 KB 0644
amd-memory-encryption.html File 26.71 KB 0644
amd_hsmp.html File 22.25 KB 0644
boot.html File 90.24 KB 0644
booting-dt.html File 13.53 KB 0644
buslock.html File 19.47 KB 0644
cpuinfo.html File 25.13 KB 0644
earlyprintk.html File 20.49 KB 0644
elf_auxvec.html File 14.44 KB 0644
entry_64.html File 17.44 KB 0644
exception-tables.html File 32.18 KB 0644
features.html File 21.74 KB 0644
ifs.html File 23.92 KB 0644
index.html File 37.18 KB 0644
intel-hfi.html File 17.6 KB 0644
intel_txt.html File 24.6 KB 0644
iommu.html File 20.98 KB 0644
kernel-stacks.html File 20.27 KB 0644
mds.html File 23.86 KB 0644
microcode.html File 23.17 KB 0644
mtrr.html File 27.58 KB 0644
orc-unwinder.html File 23.04 KB 0644
pat.html File 27.75 KB 0644
pti.html File 24.03 KB 0644
sgx.html File 52.06 KB 0644
shstk.html File 22.05 KB 0644
sva.html File 28.77 KB 0644
tdx.html File 37.07 KB 0644
tlb.html File 17.19 KB 0644
topology.html File 32.47 KB 0644
tsx_async_abort.html File 21.14 KB 0644
usb-legacy-support.html File 14.32 KB 0644
xstate.html File 20.64 KB 0644
zero-page.html File 18.08 KB 0644

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