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<section id="x86-iommu-support">
<h1><span class="section-number">16. </span>x86 IOMMU Support<a class="headerlink" href="#x86-iommu-support" title="Link to this heading">¶</a></h1>
<p>The architecture specs can be obtained from the below locations.</p>
<ul class="simple">
<li><p>Intel: <a class="reference external" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf">http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf</a></p></li>
<li><p>AMD: <a class="reference external" href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_07_PUB.pdf">https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_07_PUB.pdf</a></p></li>
</ul>
<p>This guide gives a quick cheat sheet for some basic understanding.</p>
<section id="basic-stuff">
<h2><span class="section-number">16.1. </span>Basic stuff<a class="headerlink" href="#basic-stuff" title="Link to this heading">¶</a></h2>
<p>ACPI enumerates and lists the different IOMMUs on the platform, and
device scope relationships between devices and which IOMMU controls
them.</p>
<p>Some ACPI Keywords:</p>
<ul class="simple">
<li><p>DMAR - Intel DMA Remapping table</p></li>
<li><p>DRHD - Intel DMA Remapping Hardware Unit Definition</p></li>
<li><p>RMRR - Intel Reserved Memory Region Reporting Structure</p></li>
<li><p>IVRS - AMD I/O Virtualization Reporting Structure</p></li>
<li><p>IVDB - AMD I/O Virtualization Definition Block</p></li>
<li><p>IVHD - AMD I/O Virtualization Hardware Definition</p></li>
</ul>
<section id="what-is-intel-rmrr">
<h3><span class="section-number">16.1.1. </span>What is Intel RMRR?<a class="headerlink" href="#what-is-intel-rmrr" title="Link to this heading">¶</a></h3>
<p>There are some devices the BIOS controls, for e.g USB devices to perform
PS2 emulation. The regions of memory used for these devices are marked
reserved in the e820 map. When we turn on DMA translation, DMA to those
regions will fail. Hence BIOS uses RMRR to specify these regions along with
devices that need to access these regions. OS is expected to setup
unity mappings for these regions for these devices to access these regions.</p>
</section>
<section id="what-is-amd-ivrs">
<h3><span class="section-number">16.1.2. </span>What is AMD IVRS?<a class="headerlink" href="#what-is-amd-ivrs" title="Link to this heading">¶</a></h3>
<p>The architecture defines an ACPI-compatible data structure called an I/O
Virtualization Reporting Structure (IVRS) that is used to convey information
related to I/O virtualization to system software. The IVRS describes the
configuration and capabilities of the IOMMUs contained in the platform as
well as information about the devices that each IOMMU virtualizes.</p>
<p>The IVRS provides information about the following:</p>
<ul class="simple">
<li><p>IOMMUs present in the platform including their capabilities and proper configuration</p></li>
<li><p>System I/O topology relevant to each IOMMU</p></li>
<li><p>Peripheral devices that cannot be otherwise enumerated</p></li>
<li><p>Memory regions used by SMI/SMM, platform firmware, and platform hardware. These are generally exclusion ranges to be configured by system software.</p></li>
</ul>
</section>
</section>
<section id="how-is-an-i-o-virtual-address-iova-generated">
<h2><span class="section-number">16.2. </span>How is an I/O Virtual Address (IOVA) generated?<a class="headerlink" href="#how-is-an-i-o-virtual-address-iova-generated" title="Link to this heading">¶</a></h2>
<p>Well behaved drivers call dma_map_*() calls before sending command to device
that needs to perform DMA. Once DMA is completed and mapping is no longer
required, driver performs dma_unmap_*() calls to unmap the region.</p>
</section>
<section id="intel-specific-notes">
<h2><span class="section-number">16.3. </span>Intel Specific Notes<a class="headerlink" href="#intel-specific-notes" title="Link to this heading">¶</a></h2>
<section id="graphics-problems">
<h3><span class="section-number">16.3.1. </span>Graphics Problems?<a class="headerlink" href="#graphics-problems" title="Link to this heading">¶</a></h3>
<p>If you encounter issues with graphics devices, you can try adding
option intel_iommu=igfx_off to turn off the integrated graphics engine.
If this fixes anything, please ensure you file a bug reporting the problem.</p>
</section>
<section id="some-exceptions-to-iova">
<h3><span class="section-number">16.3.2. </span>Some exceptions to IOVA<a class="headerlink" href="#some-exceptions-to-iova" title="Link to this heading">¶</a></h3>
<p>Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
The same is true for peer to peer transactions. Hence we reserve the
address from PCI MMIO ranges so they are not allocated for IOVA addresses.</p>
</section>
</section>
<section id="amd-specific-notes">
<h2><span class="section-number">16.4. </span>AMD Specific Notes<a class="headerlink" href="#amd-specific-notes" title="Link to this heading">¶</a></h2>
<section id="id1">
<h3><span class="section-number">16.4.1. </span>Graphics Problems?<a class="headerlink" href="#id1" title="Link to this heading">¶</a></h3>
<p>If you encounter issues with integrated graphics devices, you can try adding
option iommu=pt to the kernel command line use a 1:1 mapping for the IOMMU. If
this fixes anything, please ensure you file a bug reporting the problem.</p>
</section>
</section>
<section id="fault-reporting">
<h2><span class="section-number">16.5. </span>Fault reporting<a class="headerlink" href="#fault-reporting" title="Link to this heading">¶</a></h2>
<p>When errors are reported, the IOMMU signals via an interrupt. The fault
reason and device that caused it is printed on the console.</p>
</section>
<section id="kernel-log-samples">
<h2><span class="section-number">16.6. </span>Kernel Log Samples<a class="headerlink" href="#kernel-log-samples" title="Link to this heading">¶</a></h2>
<section id="intel-boot-messages">
<h3><span class="section-number">16.6.1. </span>Intel Boot Messages<a class="headerlink" href="#intel-boot-messages" title="Link to this heading">¶</a></h3>
<p>Something like this gets printed indicating presence of DMAR tables
in ACPI:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
</pre></div>
</div>
<p>When DMAR is being processed and initialized by ACPI, prints DMAR locations
and any RMRR’s processed:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>ACPI DMAR:Host address width 36
ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
</pre></div>
</div>
<p>When DMAR is enabled for use, you will notice:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>PCI-DMA: Using DMAR IOMMU
</pre></div>
</div>
</section>
<section id="intel-fault-reporting">
<h3><span class="section-number">16.6.2. </span>Intel Fault reporting<a class="headerlink" href="#intel-fault-reporting" title="Link to this heading">¶</a></h3>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
DMAR:[fault reason 05] PTE Write access is not set
DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
DMAR:[fault reason 05] PTE Write access is not set
</pre></div>
</div>
</section>
<section id="amd-boot-messages">
<h3><span class="section-number">16.6.3. </span>AMD Boot Messages<a class="headerlink" href="#amd-boot-messages" title="Link to this heading">¶</a></h3>
<p>Something like this gets printed indicating presence of the IOMMU:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>iommu: Default domain type: Translated
iommu: DMA domain TLB invalidation policy: lazy mode
</pre></div>
</div>
</section>
<section id="amd-fault-reporting">
<h3><span class="section-number">16.6.4. </span>AMD Fault reporting<a class="headerlink" href="#amd-fault-reporting" title="Link to this heading">¶</a></h3>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x0007 address=0xffffc02000 flags=0x0000]
AMD-Vi: Event logged [IO_PAGE_FAULT device=07:00.0 domain=0x0007 address=0xffffc02000 flags=0x0000]
</pre></div>
</div>
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| zero-page.html | File | 18.08 KB | 0644 |
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