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<section id="risc-v-hardware-probing-interface">
<h1>RISC-V Hardware Probing Interface<a class="headerlink" href="#risc-v-hardware-probing-interface" title="Link to this heading">¶</a></h1>
<p>The RISC-V hardware probing interface is based around a single syscall, which
is defined in <asm/hwprobe.h>:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>struct riscv_hwprobe {
__s64 key;
__u64 value;
};
long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
size_t cpusetsize, cpu_set_t *cpus,
unsigned int flags);
</pre></div>
</div>
<p>The arguments are split into three groups: an array of key-value pairs, a CPU
set, and some flags. The key-value pairs are supplied with a count. Userspace
must prepopulate the key field for each element, and the kernel will fill in the
value if the key is recognized. If a key is unknown to the kernel, its key field
will be cleared to -1, and its value set to 0. The CPU set is defined by
CPU_SET(3) with size <code class="docutils literal notranslate"><span class="pre">cpusetsize</span></code> bytes. For value-like keys (eg. vendor,
arch, impl), the returned value will only be valid if all CPUs in the given set
have the same value. Otherwise -1 will be returned. For boolean-like keys, the
value returned will be a logical AND of the values for the specified CPUs.
Usermode can supply NULL for <code class="docutils literal notranslate"><span class="pre">cpus</span></code> and 0 for <code class="docutils literal notranslate"><span class="pre">cpusetsize</span></code> as a shortcut for
all online CPUs. The currently supported flags are:</p>
<ul class="simple">
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_WHICH_CPUS</span></code>: This flag basically reverses the behavior
of <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">sys_riscv_hwprobe()</span></code>. Instead of populating the values of keys for a given
set of CPUs, the values of each key are given and the set of CPUs is reduced
by <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">sys_riscv_hwprobe()</span></code> to only those which match each of the key-value pairs.
How matching is done depends on the key type. For value-like keys, matching
means to be the exact same as the value. For boolean-like keys, matching
means the result of a logical AND of the pair’s value with the CPU’s value is
exactly the same as the pair’s value. Additionally, when <code class="docutils literal notranslate"><span class="pre">cpus</span></code> is an empty
set, then it is initialized to all online CPUs which fit within it, i.e. the
CPU set returned is the reduction of all the online CPUs which can be
represented with a CPU set of size <code class="docutils literal notranslate"><span class="pre">cpusetsize</span></code>.</p></li>
</ul>
<p>All other flags are reserved for future compatibility and must be zero.</p>
<p>On success 0 is returned, on failure a negative error code is returned.</p>
<p>The following keys are defined:</p>
<ul>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_MVENDORID</span></code>: Contains the value of <code class="docutils literal notranslate"><span class="pre">mvendorid</span></code>,
as defined by the RISC-V privileged architecture specification.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_MARCHID</span></code>: Contains the value of <code class="docutils literal notranslate"><span class="pre">marchid</span></code>, as
defined by the RISC-V privileged architecture specification.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_MIMPID</span></code>: Contains the value of <code class="docutils literal notranslate"><span class="pre">mimpid</span></code>, as
defined by the RISC-V privileged architecture specification.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_BASE_BEHAVIOR</span></code>: A bitmask containing the base
user-visible behavior that this kernel supports. The following base user ABIs
are defined:</p>
<ul class="simple">
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_BASE_BEHAVIOR_IMA</span></code>: Support for rv32ima or
rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the
privileged ISA, with the following known exceptions (more exceptions may be
added, but only if it can be demonstrated that the user ABI is not broken):</p>
<ul>
<li><p>The <code class="docutils literal notranslate"><span class="pre">fence.i</span></code> instruction cannot be directly executed by userspace
programs (it may still be executed in userspace via a
kernel-controlled mechanism such as the vDSO).</p></li>
</ul>
</li>
</ul>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_IMA_EXT_0</span></code>: A bitmask containing the extensions
that are compatible with the <code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_BASE_BEHAVIOR_IMA</span></code>:
base system behavior.</p>
<ul class="simple">
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_IMA_FD</span></code>: The F and D extensions are supported, as
defined by commit cd20cee (“FMIN/FMAX now implement
minimumNumber/maximumNumber, not minNum/maxNum”) of the RISC-V ISA manual.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_IMA_C</span></code>: The C extension is supported, as defined
by version 2.2 of the RISC-V ISA manual.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_IMA_V</span></code>: The V extension is supported, as defined by
version 1.0 of the RISC-V Vector extension manual.</p></li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBA</span></code>: The Zba address generation extension is</dt><dd><p>supported, as defined in version 1.0 of the Bit-Manipulation ISA
extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBB</span></code>: The Zbb extension is supported, as defined</dt><dd><p>in version 1.0 of the Bit-Manipulation ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBS</span></code>: The Zbs extension is supported, as defined</dt><dd><p>in version 1.0 of the Bit-Manipulation ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZICBOZ</span></code>: The Zicboz extension is supported, as</dt><dd><p>ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBC</span></code> The Zbc extension is supported, as defined</dt><dd><p>in version 1.0 of the Bit-Manipulation ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBKB</span></code> The Zbkb extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBKC</span></code> The Zbkc extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZBKX</span></code> The Zbkx extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZKND</span></code> The Zknd extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZKNE</span></code> The Zkne extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZKNH</span></code> The Zknh extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZKSED</span></code> The Zksed extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZKSH</span></code> The Zksh extension is supported, as</dt><dd><p>defined in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZKT</span></code> The Zkt extension is supported, as defined</dt><dd><p>in version 1.0 of the Scalar Crypto ISA extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVBB</span></code>: The Zvbb extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVBC</span></code>: The Zvbc extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKB</span></code>: The Zvkb extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKG</span></code>: The Zvkg extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKNED</span></code>: The Zvkned extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKNHA</span></code>: The Zvknha extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKNHB</span></code>: The Zvknhb extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKSED</span></code>: The Zvksed extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKSH</span></code>: The Zvksh extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVKT</span></code>: The Zvkt extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZFH</span></code>: The Zfh extension version 1.0 is supported</dt><dd><p>as defined in the RISC-V ISA manual.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZFHMIN</span></code>: The Zfhmin extension version 1.0 is</dt><dd><p>supported as defined in the RISC-V ISA manual.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZIHINTNTL</span></code>: The Zihintntl extension version 1.0</dt><dd><p>is supported as defined in the RISC-V ISA manual.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVFH</span></code>: The Zvfh extension is supported as</dt><dd><p>defined in the RISC-V Vector manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/e2ccd0548d6c">commit e2ccd0548d6c</a>
(“Remove draft warnings from Zvfh[min]”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVFHMIN</span></code>: The Zvfhmin extension is supported as</dt><dd><p>defined in the RISC-V Vector manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/e2ccd0548d6c">commit e2ccd0548d6c</a>
(“Remove draft warnings from Zvfh[min]”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZFA</span></code>: The Zfa extension is supported as</dt><dd><p>defined in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/056b6ff467c7">commit 056b6ff467c7</a>
(“Zfa is ratified”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZTSO</span></code>: The Ztso extension is supported as</dt><dd><p>defined in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/5618fb5a216b">commit 5618fb5a216b</a>
(“Ztso is now ratified.”)</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZACAS</span></code>: The Zacas extension is supported as</dt><dd><p>defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
from <a class="reference external" href="https://git.kernel.org/torvalds/c/5059e0ca641c">commit 5059e0ca641c</a> (“update to ratified”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZICNTR</span></code>: The Zicntr extension version 2.0</dt><dd><p>is supported as defined in the RISC-V ISA manual.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZICOND</span></code>: The Zicond extension is supported as</dt><dd><p>defined in the RISC-V Integer Conditional (Zicond) operations extension
manual starting from commit 95cf1f9 (“Add changes requested by Ved
during signoff”)</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZIHINTPAUSE</span></code>: The Zihintpause extension is</dt><dd><p>supported as defined in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/d8ab5c78c207">commit
d8ab5c78c207</a> (“Zihintpause is ratified”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZIHPM</span></code>: The Zihpm extension version 2.0</dt><dd><p>is supported as defined in the RISC-V ISA manual.</p>
</dd>
</dl>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVE32X</span></code>: The Vector sub-extension Zve32x is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVE32F</span></code>: The Vector sub-extension Zve32f is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVE64X</span></code>: The Vector sub-extension Zve64x is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVE64F</span></code>: The Vector sub-extension Zve64f is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVE64D</span></code>: The Vector sub-extension Zve64d is
supported, as defined by version 1.0 of the RISC-V Vector extension manual.</p></li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZIMOP</span></code>: The Zimop May-Be-Operations extension is</dt><dd><p>supported as defined in the RISC-V ISA manual starting from commit
58220614a5f (“Zimop is ratified/1.0”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZCA</span></code>: The Zca extension part of Zc* standard</dt><dd><p>extensions for code size reduction, as ratified in commit 8be3419c1c0
(“Zcf doesn’t exist on RV64 as it contains no instructions”) of
riscv-code-size-reduction.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZCB</span></code>: The Zcb extension part of Zc* standard</dt><dd><p>extensions for code size reduction, as ratified in commit 8be3419c1c0
(“Zcf doesn’t exist on RV64 as it contains no instructions”) of
riscv-code-size-reduction.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZCD</span></code>: The Zcd extension part of Zc* standard</dt><dd><p>extensions for code size reduction, as ratified in commit 8be3419c1c0
(“Zcf doesn’t exist on RV64 as it contains no instructions”) of
riscv-code-size-reduction.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZCF</span></code>: The Zcf extension part of Zc* standard</dt><dd><p>extensions for code size reduction, as ratified in commit 8be3419c1c0
(“Zcf doesn’t exist on RV64 as it contains no instructions”) of
riscv-code-size-reduction.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZCMOP</span></code>: The Zcmop May-Be-Operations extension is</dt><dd><p>supported as defined in the RISC-V ISA manual starting from commit
c732a4f39a4 (“Zcmop is ratified/1.0”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZAWRS</span></code>: The Zawrs extension is supported as</dt><dd><p>ratified in <a class="reference external" href="https://git.kernel.org/torvalds/c/98918c844281">commit 98918c844281</a> (“Merge pull request #1217 from
riscv/zawrs”) of riscv-isa-manual.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZAAMO</span></code>: The Zaamo extension is supported as</dt><dd><p>defined in the in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/e87412e621f1">commit e87412e621f1</a>
(“integrate Zaamo and Zalrsc text (#1304)”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZALRSC</span></code>: The Zalrsc extension is supported as</dt><dd><p>defined in the in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/e87412e621f1">commit e87412e621f1</a>
(“integrate Zaamo and Zalrsc text (#1304)”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_SUPM</span></code>: The Supm extension is supported as</dt><dd><p>defined in version 1.0 of the RISC-V Pointer Masking extensions.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZFBFMIN</span></code>: The Zfbfmin extension is supported as</dt><dd><p>defined in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/4dc23d6229de">commit 4dc23d6229de</a>
(“Added Chapter title to BF16”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVFBFMIN</span></code>: The Zvfbfmin extension is supported as</dt><dd><p>defined in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/4dc23d6229de">commit 4dc23d6229de</a>
(“Added Chapter title to BF16”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZVFBFWMA</span></code>: The Zvfbfwma extension is supported as</dt><dd><p>defined in the RISC-V ISA manual starting from <a class="reference external" href="https://git.kernel.org/torvalds/c/4dc23d6229de">commit 4dc23d6229de</a>
(“Added Chapter title to BF16”).</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZICBOM</span></code>: The Zicbom extension is supported, as</dt><dd><p>ratified in commit 3dd606f (“Create cmobase-v1.0.pdf”) of riscv-CMOs.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_EXT_ZABHA</span></code>: The Zabha extension is supported as</dt><dd><p>ratified in <a class="reference external" href="https://git.kernel.org/torvalds/c/49f49c842ff9">commit 49f49c842ff9</a> (“Update to Rafified state”) of
riscv-zabha.</p>
</dd>
</dl>
</li>
</ul>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_CPUPERF_0</span></code>: Deprecated. Returns similar values to</dt><dd><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF</span></code>, but the key was
mistakenly classified as a bitmask rather than a value.</p>
</dd>
</dl>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF</span></code>: An <code class="xref c c-enum broken_xref docutils literal notranslate"><span class="pre">enum</span> <span class="pre">value</span></code> describing
the performance of misaligned scalar native word accesses on the selected set
of processors.</p>
<ul class="simple">
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN</span></code>: The performance of
misaligned scalar accesses is unknown.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED</span></code>: Misaligned scalar
accesses are emulated via software, either in or below the kernel. These
accesses are always extremely slow.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW</span></code>: Misaligned scalar native
word sized accesses are slower than the equivalent quantity of byte
accesses. Misaligned accesses may be supported directly in hardware, or
trapped and emulated by software.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_SCALAR_FAST</span></code>: Misaligned scalar native
word sized accesses are faster than the equivalent quantity of byte
accesses.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED</span></code>: Misaligned scalar
accesses are not supported at all and will generate a misaligned address
fault.</p></li>
</ul>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE</span></code>: An unsigned int which
represents the size of the Zicboz block in bytes.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS</span></code>: An unsigned long which
represent the highest userspace virtual address usable.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_TIME_CSR_FREQ</span></code>: Frequency (in Hz) of <cite>time CSR</cite>.</p></li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF</span></code>: An enum value describing the</dt><dd><p>performance of misaligned vector accesses on the selected set of processors.</p>
</dd>
</dl>
<ul class="simple">
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN</span></code>: The performance of misaligned
vector accesses is unknown.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW</span></code>: 32-bit misaligned accesses using vector
registers are slower than the equivalent quantity of byte accesses via vector registers.
Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_VECTOR_FAST</span></code>: 32-bit misaligned accesses using vector
registers are faster than the equivalent quantity of byte accesses via vector registers.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED</span></code>: Misaligned vector accesses are
not supported at all and will generate a misaligned address fault.</p></li>
</ul>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0</span></code>: A bitmask containing the
mips vendor extensions that are compatible with the
<code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_BASE_BEHAVIOR_IMA</span></code>: base system behavior.</p>
<ul class="simple">
<li><p>MIPS</p>
<ul>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL</span></code>: The xmipsexectl vendor</dt><dd><p>extension is supported in the MIPS ISA extensions spec.</p>
</dd>
</dl>
</li>
</ul>
</li>
</ul>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0</span></code>: A bitmask containing the
thead vendor extensions that are compatible with the
<code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_BASE_BEHAVIOR_IMA</span></code>: base system behavior.</p>
<ul class="simple">
<li><p>T-HEAD</p>
<ul>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR</span></code>: The xtheadvector vendor</dt><dd><p>extension is supported in the T-Head ISA extensions spec starting from
commit a18c801634 (“Add T-Head VECTOR vendor extension. “).</p>
</dd>
</dl>
</li>
</ul>
</li>
</ul>
</li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE</span></code>: An unsigned int which
represents the size of the Zicbom block in bytes.</p></li>
<li><p><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0</span></code>: A bitmask containing the
sifive vendor extensions that are compatible with the
<code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_BASE_BEHAVIOR_IMA</span></code>: base system behavior.</p>
<ul class="simple">
<li><p>SIFIVE</p>
<ul>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD</span></code>: The Xsfqmaccdod vendor</dt><dd><p>extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
Extensions Specification.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ</span></code>: The Xsfqmaccqoq vendor</dt><dd><p>extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
Instruction Extensions Specification.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF</span></code>: The Xsfvfnrclipxfqf</dt><dd><p>vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
Clip Instructions Extensions Specification.</p>
</dd>
</dl>
</li>
<li><dl class="simple">
<dt><code class="xref c c-macro docutils literal notranslate"><span class="pre">RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ</span></code>: The Xsfvfwmaccqqq</dt><dd><p>vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
Instruction Extensions Specification.</p>
</dd>
</dl>
</li>
</ul>
</li>
</ul>
</li>
</ul>
</section>
</div>
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