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<section id="introduction-to-loongarch">
<h1><span class="section-number">1. </span>Introduction to LoongArch<a class="headerlink" href="#introduction-to-loongarch" title="Link to this heading">¶</a></h1>
<p>LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0
while applications run at PLV3. This document introduces the registers, basic
instruction set, virtual memory and some other topics of LoongArch.</p>
<section id="registers">
<h2><span class="section-number">1.1. </span>Registers<a class="headerlink" href="#registers" title="Link to this heading">¶</a></h2>
<p>LoongArch registers include general purpose registers (GPRs), floating point
registers (FPRs), vector registers (VRs) and control status registers (CSRs)
used in privileged mode (PLV0).</p>
<section id="gprs">
<h3><span class="section-number">1.1.1. </span>GPRs<a class="headerlink" href="#gprs" title="Link to this heading">¶</a></h3>
<p>LoongArch has 32 GPRs ( <code class="docutils literal notranslate"><span class="pre">$r0</span></code> ~ <code class="docutils literal notranslate"><span class="pre">$r31</span></code> ); each one is 32-bit wide in LA32
and 64-bit wide in LA64. <code class="docutils literal notranslate"><span class="pre">$r0</span></code> is hard-wired to zero, and the other registers
are not architecturally special. (Except <code class="docutils literal notranslate"><span class="pre">$r1</span></code>, which is hard-wired as the
link register of the BL instruction.)</p>
<p>The kernel uses a variant of the LoongArch register convention, as described in
the LoongArch ELF psABI spec, in <a class="reference internal" href="#loongarch-references"><span class="std std-ref">References</span></a>:</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Name</p></th>
<th class="head"><p>Alias</p></th>
<th class="head"><p>Usage</p></th>
<th class="head"><p>Preserved
across calls</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$r0</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$zero</span></code></p></td>
<td><p>Constant zero</p></td>
<td><p>Unused</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$r1</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$ra</span></code></p></td>
<td><p>Return address</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$r2</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$tp</span></code></p></td>
<td><p>TLS/Thread pointer</p></td>
<td><p>Unused</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$r3</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$sp</span></code></p></td>
<td><p>Stack pointer</p></td>
<td><p>Yes</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$r4</span></code>-<code class="docutils literal notranslate"><span class="pre">$r11</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$a0</span></code>-<code class="docutils literal notranslate"><span class="pre">$a7</span></code></p></td>
<td><p>Argument registers</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$r4</span></code>-<code class="docutils literal notranslate"><span class="pre">$r5</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$v0</span></code>-<code class="docutils literal notranslate"><span class="pre">$v1</span></code></p></td>
<td><p>Return value</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$r12</span></code>-<code class="docutils literal notranslate"><span class="pre">$r20</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$t0</span></code>-<code class="docutils literal notranslate"><span class="pre">$t8</span></code></p></td>
<td><p>Temp registers</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$r21</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$u0</span></code></p></td>
<td><p>Percpu base address</p></td>
<td><p>Unused</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$r22</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$fp</span></code></p></td>
<td><p>Frame pointer</p></td>
<td><p>Yes</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$r23</span></code>-<code class="docutils literal notranslate"><span class="pre">$r31</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$s0</span></code>-<code class="docutils literal notranslate"><span class="pre">$s8</span></code></p></td>
<td><p>Static registers</p></td>
<td><p>Yes</p></td>
</tr>
</tbody>
</table>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>The register <code class="docutils literal notranslate"><span class="pre">$r21</span></code> is reserved in the ELF psABI, but used by the Linux
kernel for storing the percpu base address. It normally has no ABI name,
but is called <code class="docutils literal notranslate"><span class="pre">$u0</span></code> in the kernel. You may also see <code class="docutils literal notranslate"><span class="pre">$v0</span></code> or <code class="docutils literal notranslate"><span class="pre">$v1</span></code>
in some old code,however they are deprecated aliases of <code class="docutils literal notranslate"><span class="pre">$a0</span></code> and <code class="docutils literal notranslate"><span class="pre">$a1</span></code>
respectively.</p>
</div>
</section>
<section id="fprs">
<h3><span class="section-number">1.1.2. </span>FPRs<a class="headerlink" href="#fprs" title="Link to this heading">¶</a></h3>
<p>LoongArch has 32 FPRs ( <code class="docutils literal notranslate"><span class="pre">$f0</span></code> ~ <code class="docutils literal notranslate"><span class="pre">$f31</span></code> ) when FPU is present. Each one is
64-bit wide on the LA64 cores.</p>
<p>The floating-point register convention is the same as described in the
LoongArch ELF psABI spec:</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Name</p></th>
<th class="head"><p>Alias</p></th>
<th class="head"><p>Usage</p></th>
<th class="head"><p>Preserved
across calls</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$f0</span></code>-<code class="docutils literal notranslate"><span class="pre">$f7</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$fa0</span></code>-<code class="docutils literal notranslate"><span class="pre">$fa7</span></code></p></td>
<td><p>Argument registers</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$f0</span></code>-<code class="docutils literal notranslate"><span class="pre">$f1</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$fv0</span></code>-<code class="docutils literal notranslate"><span class="pre">$fv1</span></code></p></td>
<td><p>Return value</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">$f8</span></code>-<code class="docutils literal notranslate"><span class="pre">$f23</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$ft0</span></code>-<code class="docutils literal notranslate"><span class="pre">$ft15</span></code></p></td>
<td><p>Temp registers</p></td>
<td><p>No</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">$f24</span></code>-<code class="docutils literal notranslate"><span class="pre">$f31</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">$fs0</span></code>-<code class="docutils literal notranslate"><span class="pre">$fs7</span></code></p></td>
<td><p>Static registers</p></td>
<td><p>Yes</p></td>
</tr>
</tbody>
</table>
<div class="admonition note">
<p class="admonition-title">Note</p>
<p>You may see <code class="docutils literal notranslate"><span class="pre">$fv0</span></code> or <code class="docutils literal notranslate"><span class="pre">$fv1</span></code> in some old code, however they are
deprecated aliases of <code class="docutils literal notranslate"><span class="pre">$fa0</span></code> and <code class="docutils literal notranslate"><span class="pre">$fa1</span></code> respectively.</p>
</div>
</section>
<section id="vrs">
<h3><span class="section-number">1.1.3. </span>VRs<a class="headerlink" href="#vrs" title="Link to this heading">¶</a></h3>
<p>There are currently 2 vector extensions to LoongArch:</p>
<ul class="simple">
<li><p>LSX (Loongson SIMD eXtension) with 128-bit vectors,</p></li>
<li><p>LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors.</p></li>
</ul>
<p>LSX brings <code class="docutils literal notranslate"><span class="pre">$v0</span></code> ~ <code class="docutils literal notranslate"><span class="pre">$v31</span></code> while LASX brings <code class="docutils literal notranslate"><span class="pre">$x0</span></code> ~ <code class="docutils literal notranslate"><span class="pre">$x31</span></code> as the vector
registers.</p>
<p>The VRs overlap with FPRs: for example, on a core implementing LSX and LASX,
the lower 128 bits of <code class="docutils literal notranslate"><span class="pre">$x0</span></code> is shared with <code class="docutils literal notranslate"><span class="pre">$v0</span></code>, and the lower 64 bits of
<code class="docutils literal notranslate"><span class="pre">$v0</span></code> is shared with <code class="docutils literal notranslate"><span class="pre">$f0</span></code>; same with all other VRs.</p>
</section>
<section id="csrs">
<h3><span class="section-number">1.1.4. </span>CSRs<a class="headerlink" href="#csrs" title="Link to this heading">¶</a></h3>
<p>CSRs can only be accessed from privileged mode (PLV0):</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Address</p></th>
<th class="head"><p>Full Name</p></th>
<th class="head"><p>Abbrev Name</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>0x0</p></td>
<td><p>Current Mode Information</p></td>
<td><p>CRMD</p></td>
</tr>
<tr class="row-odd"><td><p>0x1</p></td>
<td><p>Pre-exception Mode Information</p></td>
<td><p>PRMD</p></td>
</tr>
<tr class="row-even"><td><p>0x2</p></td>
<td><p>Extension Unit Enable</p></td>
<td><p>EUEN</p></td>
</tr>
<tr class="row-odd"><td><p>0x3</p></td>
<td><p>Miscellaneous Control</p></td>
<td><p>MISC</p></td>
</tr>
<tr class="row-even"><td><p>0x4</p></td>
<td><p>Exception Configuration</p></td>
<td><p>ECFG</p></td>
</tr>
<tr class="row-odd"><td><p>0x5</p></td>
<td><p>Exception Status</p></td>
<td><p>ESTAT</p></td>
</tr>
<tr class="row-even"><td><p>0x6</p></td>
<td><p>Exception Return Address</p></td>
<td><p>ERA</p></td>
</tr>
<tr class="row-odd"><td><p>0x7</p></td>
<td><p>Bad (Faulting) Virtual Address</p></td>
<td><p>BADV</p></td>
</tr>
<tr class="row-even"><td><p>0x8</p></td>
<td><p>Bad (Faulting) Instruction Word</p></td>
<td><p>BADI</p></td>
</tr>
<tr class="row-odd"><td><p>0xC</p></td>
<td><p>Exception Entrypoint Address</p></td>
<td><p>EENTRY</p></td>
</tr>
<tr class="row-even"><td><p>0x10</p></td>
<td><p>TLB Index</p></td>
<td><p>TLBIDX</p></td>
</tr>
<tr class="row-odd"><td><p>0x11</p></td>
<td><p>TLB Entry High-order Bits</p></td>
<td><p>TLBEHI</p></td>
</tr>
<tr class="row-even"><td><p>0x12</p></td>
<td><p>TLB Entry Low-order Bits 0</p></td>
<td><p>TLBELO0</p></td>
</tr>
<tr class="row-odd"><td><p>0x13</p></td>
<td><p>TLB Entry Low-order Bits 1</p></td>
<td><p>TLBELO1</p></td>
</tr>
<tr class="row-even"><td><p>0x18</p></td>
<td><p>Address Space Identifier</p></td>
<td><p>ASID</p></td>
</tr>
<tr class="row-odd"><td><p>0x19</p></td>
<td><p>Page Global Directory Address for
Lower-half Address Space</p></td>
<td><p>PGDL</p></td>
</tr>
<tr class="row-even"><td><p>0x1A</p></td>
<td><p>Page Global Directory Address for
Higher-half Address Space</p></td>
<td><p>PGDH</p></td>
</tr>
<tr class="row-odd"><td><p>0x1B</p></td>
<td><p>Page Global Directory Address</p></td>
<td><p>PGD</p></td>
</tr>
<tr class="row-even"><td><p>0x1C</p></td>
<td><p>Page Walk Control for Lower-
half Address Space</p></td>
<td><p>PWCL</p></td>
</tr>
<tr class="row-odd"><td><p>0x1D</p></td>
<td><p>Page Walk Control for Higher-
half Address Space</p></td>
<td><p>PWCH</p></td>
</tr>
<tr class="row-even"><td><p>0x1E</p></td>
<td><p>STLB Page Size</p></td>
<td><p>STLBPS</p></td>
</tr>
<tr class="row-odd"><td><p>0x1F</p></td>
<td><p>Reduced Virtual Address Configuration</p></td>
<td><p>RVACFG</p></td>
</tr>
<tr class="row-even"><td><p>0x20</p></td>
<td><p>CPU Identifier</p></td>
<td><p>CPUID</p></td>
</tr>
<tr class="row-odd"><td><p>0x21</p></td>
<td><p>Privileged Resource Configuration 1</p></td>
<td><p>PRCFG1</p></td>
</tr>
<tr class="row-even"><td><p>0x22</p></td>
<td><p>Privileged Resource Configuration 2</p></td>
<td><p>PRCFG2</p></td>
</tr>
<tr class="row-odd"><td><p>0x23</p></td>
<td><p>Privileged Resource Configuration 3</p></td>
<td><p>PRCFG3</p></td>
</tr>
<tr class="row-even"><td><p>0x30+n (0≤n≤15)</p></td>
<td><p>Saved Data register</p></td>
<td><p>SAVEn</p></td>
</tr>
<tr class="row-odd"><td><p>0x40</p></td>
<td><p>Timer Identifier</p></td>
<td><p>TID</p></td>
</tr>
<tr class="row-even"><td><p>0x41</p></td>
<td><p>Timer Configuration</p></td>
<td><p>TCFG</p></td>
</tr>
<tr class="row-odd"><td><p>0x42</p></td>
<td><p>Timer Value</p></td>
<td><p>TVAL</p></td>
</tr>
<tr class="row-even"><td><p>0x43</p></td>
<td><p>Compensation of Timer Count</p></td>
<td><p>CNTC</p></td>
</tr>
<tr class="row-odd"><td><p>0x44</p></td>
<td><p>Timer Interrupt Clearing</p></td>
<td><p>TICLR</p></td>
</tr>
<tr class="row-even"><td><p>0x60</p></td>
<td><p>LLBit Control</p></td>
<td><p>LLBCTL</p></td>
</tr>
<tr class="row-odd"><td><p>0x80</p></td>
<td><p>Implementation-specific Control 1</p></td>
<td><p>IMPCTL1</p></td>
</tr>
<tr class="row-even"><td><p>0x81</p></td>
<td><p>Implementation-specific Control 2</p></td>
<td><p>IMPCTL2</p></td>
</tr>
<tr class="row-odd"><td><p>0x88</p></td>
<td><p>TLB Refill Exception Entrypoint
Address</p></td>
<td><p>TLBRENTRY</p></td>
</tr>
<tr class="row-even"><td><p>0x89</p></td>
<td><p>TLB Refill Exception BAD (Faulting)
Virtual Address</p></td>
<td><p>TLBRBADV</p></td>
</tr>
<tr class="row-odd"><td><p>0x8A</p></td>
<td><p>TLB Refill Exception Return Address</p></td>
<td><p>TLBRERA</p></td>
</tr>
<tr class="row-even"><td><p>0x8B</p></td>
<td><p>TLB Refill Exception Saved Data
Register</p></td>
<td><p>TLBRSAVE</p></td>
</tr>
<tr class="row-odd"><td><p>0x8C</p></td>
<td><p>TLB Refill Exception Entry Low-order
Bits 0</p></td>
<td><p>TLBRELO0</p></td>
</tr>
<tr class="row-even"><td><p>0x8D</p></td>
<td><p>TLB Refill Exception Entry Low-order
Bits 1</p></td>
<td><p>TLBRELO1</p></td>
</tr>
<tr class="row-odd"><td><p>0x8E</p></td>
<td><p>TLB Refill Exception Entry High-order
Bits</p></td>
<td><p>TLBEHI</p></td>
</tr>
<tr class="row-even"><td><p>0x8F</p></td>
<td><p>TLB Refill Exception Pre-exception
Mode Information</p></td>
<td><p>TLBRPRMD</p></td>
</tr>
<tr class="row-odd"><td><p>0x90</p></td>
<td><p>Machine Error Control</p></td>
<td><p>MERRCTL</p></td>
</tr>
<tr class="row-even"><td><p>0x91</p></td>
<td><p>Machine Error Information 1</p></td>
<td><p>MERRINFO1</p></td>
</tr>
<tr class="row-odd"><td><p>0x92</p></td>
<td><p>Machine Error Information 2</p></td>
<td><p>MERRINFO2</p></td>
</tr>
<tr class="row-even"><td><p>0x93</p></td>
<td><p>Machine Error Exception Entrypoint
Address</p></td>
<td><p>MERRENTRY</p></td>
</tr>
<tr class="row-odd"><td><p>0x94</p></td>
<td><p>Machine Error Exception Return
Address</p></td>
<td><p>MERRERA</p></td>
</tr>
<tr class="row-even"><td><p>0x95</p></td>
<td><p>Machine Error Exception Saved Data
Register</p></td>
<td><p>MERRSAVE</p></td>
</tr>
<tr class="row-odd"><td><p>0x98</p></td>
<td><p>Cache TAGs</p></td>
<td><p>CTAG</p></td>
</tr>
<tr class="row-even"><td><p>0x180+n (0≤n≤3)</p></td>
<td><p>Direct Mapping Configuration Window n</p></td>
<td><p>DMWn</p></td>
</tr>
<tr class="row-odd"><td><p>0x200+2n (0≤n≤31)</p></td>
<td><p>Performance Monitor Configuration n</p></td>
<td><p>PMCFGn</p></td>
</tr>
<tr class="row-even"><td><p>0x201+2n (0≤n≤31)</p></td>
<td><p>Performance Monitor Overall Counter n</p></td>
<td><p>PMCNTn</p></td>
</tr>
<tr class="row-odd"><td><p>0x300</p></td>
<td><p>Memory Load/Store WatchPoint
Overall Control</p></td>
<td><p>MWPC</p></td>
</tr>
<tr class="row-even"><td><p>0x301</p></td>
<td><p>Memory Load/Store WatchPoint
Overall Status</p></td>
<td><p>MWPS</p></td>
</tr>
<tr class="row-odd"><td><p>0x310+8n (0≤n≤7)</p></td>
<td><p>Memory Load/Store WatchPoint n
Configuration 1</p></td>
<td><p>MWPnCFG1</p></td>
</tr>
<tr class="row-even"><td><p>0x311+8n (0≤n≤7)</p></td>
<td><p>Memory Load/Store WatchPoint n
Configuration 2</p></td>
<td><p>MWPnCFG2</p></td>
</tr>
<tr class="row-odd"><td><p>0x312+8n (0≤n≤7)</p></td>
<td><p>Memory Load/Store WatchPoint n
Configuration 3</p></td>
<td><p>MWPnCFG3</p></td>
</tr>
<tr class="row-even"><td><p>0x313+8n (0≤n≤7)</p></td>
<td><p>Memory Load/Store WatchPoint n
Configuration 4</p></td>
<td><p>MWPnCFG4</p></td>
</tr>
<tr class="row-odd"><td><p>0x380</p></td>
<td><p>Instruction Fetch WatchPoint
Overall Control</p></td>
<td><p>FWPC</p></td>
</tr>
<tr class="row-even"><td><p>0x381</p></td>
<td><p>Instruction Fetch WatchPoint
Overall Status</p></td>
<td><p>FWPS</p></td>
</tr>
<tr class="row-odd"><td><p>0x390+8n (0≤n≤7)</p></td>
<td><p>Instruction Fetch WatchPoint n
Configuration 1</p></td>
<td><p>FWPnCFG1</p></td>
</tr>
<tr class="row-even"><td><p>0x391+8n (0≤n≤7)</p></td>
<td><p>Instruction Fetch WatchPoint n
Configuration 2</p></td>
<td><p>FWPnCFG2</p></td>
</tr>
<tr class="row-odd"><td><p>0x392+8n (0≤n≤7)</p></td>
<td><p>Instruction Fetch WatchPoint n
Configuration 3</p></td>
<td><p>FWPnCFG3</p></td>
</tr>
<tr class="row-even"><td><p>0x393+8n (0≤n≤7)</p></td>
<td><p>Instruction Fetch WatchPoint n
Configuration 4</p></td>
<td><p>FWPnCFG4</p></td>
</tr>
<tr class="row-odd"><td><p>0x500</p></td>
<td><p>Debug Register</p></td>
<td><p>DBG</p></td>
</tr>
<tr class="row-even"><td><p>0x501</p></td>
<td><p>Debug Exception Return Address</p></td>
<td><p>DERA</p></td>
</tr>
<tr class="row-odd"><td><p>0x502</p></td>
<td><p>Debug Exception Saved Data Register</p></td>
<td><p>DSAVE</p></td>
</tr>
</tbody>
</table>
<p>ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC
and DEPC respectively.</p>
</section>
</section>
<section id="basic-instruction-set">
<h2><span class="section-number">1.2. </span>Basic Instruction Set<a class="headerlink" href="#basic-instruction-set" title="Link to this heading">¶</a></h2>
<section id="instruction-formats">
<h3><span class="section-number">1.2.1. </span>Instruction formats<a class="headerlink" href="#instruction-formats" title="Link to this heading">¶</a></h3>
<p>LoongArch instructions are 32 bits wide, belonging to 9 basic instruction
formats (and variants of them):</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Format name</p></th>
<th class="head"><p>Composition</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>2R</p></td>
<td><p>Opcode + Rj + Rd</p></td>
</tr>
<tr class="row-odd"><td><p>3R</p></td>
<td><p>Opcode + Rk + Rj + Rd</p></td>
</tr>
<tr class="row-even"><td><p>4R</p></td>
<td><p>Opcode + Ra + Rk + Rj + Rd</p></td>
</tr>
<tr class="row-odd"><td><p>2RI8</p></td>
<td><p>Opcode + I8 + Rj + Rd</p></td>
</tr>
<tr class="row-even"><td><p>2RI12</p></td>
<td><p>Opcode + I12 + Rj + Rd</p></td>
</tr>
<tr class="row-odd"><td><p>2RI14</p></td>
<td><p>Opcode + I14 + Rj + Rd</p></td>
</tr>
<tr class="row-even"><td><p>2RI16</p></td>
<td><p>Opcode + I16 + Rj + Rd</p></td>
</tr>
<tr class="row-odd"><td><p>1RI21</p></td>
<td><p>Opcode + I21L + Rj + I21H</p></td>
</tr>
<tr class="row-even"><td><p>I26</p></td>
<td><p>Opcode + I26L + I26H</p></td>
</tr>
</tbody>
</table>
<p>Rd is the destination register operand, while Rj, Rk and Ra (“a” stands for
“additional”) are the source register operands. I8/I12/I14/I16/I21/I26 are
immediate operands of respective width. The longer I21 and I26 are stored
in separate higher and lower parts in the instruction word, denoted by the “L”
and “H” suffixes.</p>
</section>
<section id="list-of-instructions">
<h3><span class="section-number">1.2.2. </span>List of Instructions<a class="headerlink" href="#list-of-instructions" title="Link to this heading">¶</a></h3>
<p>For brevity, only instruction names (mnemonics) are listed here; please see the
<a class="reference internal" href="#loongarch-references"><span class="std std-ref">References</span></a> for details.</p>
<ol class="arabic">
<li><p>Arithmetic Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
SLT SLTU SLTI SLTUI
AND OR NOR XOR ANDN ORN ANDI ORI XORI
MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
PCADDI PCADDU12I PCADDU18I
LU12I.W LU32I.D LU52I.D ADDU16I.D
</pre></div>
</div>
</li>
<li><p>Bit-shift Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
</pre></div>
</div>
</li>
<li><p>Bit-manipulation Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
MASKEQZ MASKNEZ
</pre></div>
</div>
</li>
<li><p>Branch Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
</pre></div>
</div>
</li>
<li><p>Load/Store Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
LDPTR.W LDPTR.D STPTR.W STPTR.D
PRELD PRELDX
</pre></div>
</div>
</li>
<li><p>Atomic Operation Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>LL.W SC.W LL.D SC.D
AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
AMMAX.W AMMAX.D AMMIN.W AMMIN.D
</pre></div>
</div>
</li>
<li><p>Barrier Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>IBAR DBAR
</pre></div>
</div>
</li>
<li><p>Special Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
ASRTLE.D ASRTGT.D
</pre></div>
</div>
</li>
<li><p>Privileged Instructions:</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>CSRRD CSRWR CSRXCHG
IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
</pre></div>
</div>
</li>
</ol>
</section>
</section>
<section id="virtual-memory">
<h2><span class="section-number">1.3. </span>Virtual Memory<a class="headerlink" href="#virtual-memory" title="Link to this heading">¶</a></h2>
<p>LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.</p>
<p>Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple
relationship between virtual address (VA) and physical address (PA):</p>
<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>VA = PA + FixedOffset
</pre></div>
</div>
<p>Page-mapped virtual memory has arbitrary relationship between VA and PA, which
is recorded in TLB and page tables. LoongArch’s TLB includes a fully-associative
MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB).</p>
<p>By default, the whole virtual address space of LA32 is configured like this:</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Name</p></th>
<th class="head"><p>Address Range</p></th>
<th class="head"><p>Attributes</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">UVRANGE</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0x00000000</span> <span class="pre">-</span> <span class="pre">0x7FFFFFFF</span></code></p></td>
<td><p>Page-mapped, Cached, PLV0~3</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">KPRANGE0</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0x80000000</span> <span class="pre">-</span> <span class="pre">0x9FFFFFFF</span></code></p></td>
<td><p>Direct-mapped, Uncached, PLV0</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">KPRANGE1</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0xA0000000</span> <span class="pre">-</span> <span class="pre">0xBFFFFFFF</span></code></p></td>
<td><p>Direct-mapped, Cached, PLV0</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">KVRANGE</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0xC0000000</span> <span class="pre">-</span> <span class="pre">0xFFFFFFFF</span></code></p></td>
<td><p>Page-mapped, Cached, PLV0</p></td>
</tr>
</tbody>
</table>
<p>User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and
KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached
direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped
VA of 0x00001000 is 0xA0001000.</p>
<p>By default, the whole virtual address space of LA64 is configured like this:</p>
<table class="docutils align-default">
<thead>
<tr class="row-odd"><th class="head"><p>Name</p></th>
<th class="head"><p>Address Range</p></th>
<th class="head"><p>Attributes</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">XUVRANGE</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0x0000000000000000</span> <span class="pre">-</span>
<span class="pre">0x3FFFFFFFFFFFFFFF</span></code></p></td>
<td><p>Page-mapped, Cached, PLV0~3</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">XSPRANGE</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0x4000000000000000</span> <span class="pre">-</span>
<span class="pre">0x7FFFFFFFFFFFFFFF</span></code></p></td>
<td><p>Direct-mapped, Cached / Uncached, PLV0</p></td>
</tr>
<tr class="row-even"><td><p><code class="docutils literal notranslate"><span class="pre">XKPRANGE</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0x8000000000000000</span> <span class="pre">-</span>
<span class="pre">0xBFFFFFFFFFFFFFFF</span></code></p></td>
<td><p>Direct-mapped, Cached / Uncached, PLV0</p></td>
</tr>
<tr class="row-odd"><td><p><code class="docutils literal notranslate"><span class="pre">XKVRANGE</span></code></p></td>
<td><p><code class="docutils literal notranslate"><span class="pre">0xC000000000000000</span> <span class="pre">-</span>
<span class="pre">0xFFFFFFFFFFFFFFFF</span></code></p></td>
<td><p>Page-mapped, Cached, PLV0</p></td>
</tr>
</tbody>
</table>
<p>User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and
XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute
is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is
for coherent cached, and 2 is for weakly-ordered uncached.</p>
<p>Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved.</p>
<p>To put this in action: the strongly-ordered uncached direct-mapped VA (in
XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached
direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000,
and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000
_00001000 is 0xA0000000_00001000.</p>
</section>
<section id="relationship-of-loongson-and-loongarch">
<h2><span class="section-number">1.4. </span>Relationship of Loongson and LoongArch<a class="headerlink" href="#relationship-of-loongson-and-loongarch" title="Link to this heading">¶</a></h2>
<p>LoongArch is a RISC ISA which is different from any other existing ones, while
Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is
the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,
and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on
MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:
Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-
3A5000 (and future revisions) are all based on LoongArch.</p>
</section>
<section id="references">
<span id="loongarch-references"></span><h2><span class="section-number">1.5. </span>References<a class="headerlink" href="#references" title="Link to this heading">¶</a></h2>
<p>Official web site of Loongson Technology Corp. Ltd.:</p>
<blockquote>
<div><p><a class="reference external" href="http://www.loongson.cn/">http://www.loongson.cn/</a></p>
</div></blockquote>
<p>Developer web site of Loongson and LoongArch (Software and Documentation):</p>
<blockquote>
<div><p><a class="reference external" href="http://www.loongnix.cn/">http://www.loongnix.cn/</a></p>
<p><a class="reference external" href="https://github.com/loongson/">https://github.com/loongson/</a></p>
<p><a class="reference external" href="https://loongson.github.io/LoongArch-Documentation/">https://loongson.github.io/LoongArch-Documentation/</a></p>
</div></blockquote>
<p>Documentation of LoongArch ISA:</p>
<blockquote>
<div><p><a class="reference external" href="https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-CN.pdf">https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-CN.pdf</a> (in Chinese)</p>
<p><a class="reference external" href="https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-EN.pdf">https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.10-EN.pdf</a> (in English)</p>
</div></blockquote>
<p>Documentation of LoongArch ELF psABI:</p>
<blockquote>
<div><p><a class="reference external" href="https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.01-CN.pdf">https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.01-CN.pdf</a> (in Chinese)</p>
<p><a class="reference external" href="https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.01-EN.pdf">https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v2.01-EN.pdf</a> (in English)</p>
</div></blockquote>
<p>Linux kernel repository of Loongson and LoongArch:</p>
<blockquote>
<div><p><a class="reference external" href="https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git">https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git</a></p>
</div></blockquote>
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